 mrg
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a145a37cf7
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PEP8 fixes in regress.py
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2020-10-05 15:56:12 -07:00 |
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mrg
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cb35c0aff4
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Add command line -j option for number of threads.
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2020-10-05 15:49:00 -07:00 |
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mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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mrg
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c4952ca8be
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Skip full sram pex test too slow
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2020-10-05 13:51:20 -07:00 |
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mrg
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9fe6358569
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Change .spinit to .spiceinit
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2020-10-05 13:50:04 -07:00 |
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mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
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64cc620440
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Add sram pex test
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2020-10-02 14:55:10 -07:00 |
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mrg
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1fc4040607
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Add pand4 and pnand4
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2020-10-02 14:54:12 -07:00 |
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mrg
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a62b82128c
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Skip riscv func test because too slow
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2020-10-02 13:33:58 -07:00 |
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mrg
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1e24b780bb
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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mrg
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b32c123dab
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PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
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2020-10-01 11:10:18 -07:00 |
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mrg
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18c8ad265e
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Unique name for sram channel routes
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2020-10-01 09:55:34 -07:00 |
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mrg
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aaa36bf5cf
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Default to 2 threads only
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2020-10-01 09:55:17 -07:00 |
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mrg
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d315ff18e5
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Add num_threads to options. PEP8 cleanup.
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2020-10-01 08:07:03 -07:00 |
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mrg
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b81cdab0d6
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Use unique instance names for channel routes.
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2020-10-01 07:43:06 -07:00 |
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mrg
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8ce23d7f17
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Provide unique WL driver instance name
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2020-10-01 07:17:32 -07:00 |
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mrg
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bd125e2ed3
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Check for duplicate instance names.
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2020-10-01 07:17:16 -07:00 |
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Matt Guthaus
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2b475670f7
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Check for failed result in functional simulation
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2020-09-30 12:40:07 -07:00 |
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Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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f4e6a8895b
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Update riscv unit test
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2020-09-30 08:50:58 -07:00 |
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mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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mrg
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066570bfeb
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Fix length of write driver
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2020-09-29 16:51:55 -07:00 |
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mrg
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8e908f016e
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PEP8 formatting
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2020-09-29 13:43:59 -07:00 |
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mrg
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bca69b24e3
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Optional number of functional cycles
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2020-09-29 13:43:54 -07:00 |
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mrg
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54890a8d77
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Add new golden data
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2020-09-29 13:43:34 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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mrg
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0c280e062a
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Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.
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2020-09-29 11:35:58 -07:00 |
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mrg
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4b5bbe755f
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PEP8 cleanup. Fix cur_slew bug.
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2020-09-29 11:13:58 -07:00 |
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mrg
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9032bb9869
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Add global wordline delay test
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2020-09-29 10:28:57 -07:00 |
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mrg
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d7e2340e62
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Lots of PEP8 cleanup. Refactor path graph to simulation class.
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2020-09-29 10:26:31 -07:00 |
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mrg
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1eb8798bb6
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Add global functional test
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2020-09-28 16:12:09 -07:00 |
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mrg
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b2dab486fc
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Add draft of path exclusion calls
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2020-09-28 16:05:21 -07:00 |
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mrg
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4a987bef9a
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Merge branch 'wlbuffer' into dev
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2020-09-28 15:51:45 -07:00 |
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mrg
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159c04a25d
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-09-28 15:51:35 -07:00 |
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mrg
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70c90ca7fb
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Replica bitcell array bbox to include unused WL gnd pins.
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2020-09-28 14:49:33 -07:00 |
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mrg
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9c6d8d7aed
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Zjob to bottom.
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2020-09-28 13:16:03 -07:00 |
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mrg
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5ab0d01779
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Remove zjog and go with L shape.
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2020-09-28 12:48:37 -07:00 |
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mrg
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d65eb16513
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Zjog the WL enable. Min driver is 1.
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2020-09-28 12:24:55 -07:00 |
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mrg
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6f06bb9dd5
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Create sized RBL WL driver in port_address
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2020-09-28 11:30:21 -07:00 |
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mrg
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88731ccd8e
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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mrg
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c7d32089f3
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Create RBL wordline buffer with correct polarity.
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2020-09-17 14:45:49 -07:00 |
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mrg
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392afd4d4b
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Add unit test for hierarchical wordline.
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2020-09-15 13:46:21 -07:00 |
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mrg
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11f2b6b809
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Do not do final verification if supplies were not routed
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2020-09-15 13:39:00 -07:00 |
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mrg
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e7ad22ff69
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Separate WL via from bitell array to avoid grounded WLs
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2020-09-15 13:38:28 -07:00 |
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mrg
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5e94d76127
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Make global bitline only as wide as needed rather than whole array
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2020-09-15 13:24:38 -07:00 |
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mrg
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aff3cd2aab
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Update length of control bus
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2020-09-15 09:49:00 -07:00 |
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mrg
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f25b6ffa61
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Make control bus height of port data
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2020-09-14 15:42:17 -07:00 |
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mrg
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7b24d1f012
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Use pins for write_driver dimensions
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2020-09-14 14:42:28 -07:00 |
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