2232 Commits

Author	SHA1	Message	Date
mrg	355474ce2c	Playing around with pnand2 pin spacing rules	2020-06-15 10:07:00 -07:00
mrg	6e0008403e	Update new tech name	2020-06-15 10:06:17 -07:00
mrg	79b3b9a8b0	Switch input/output layers for predecodes	2020-06-15 10:06:04 -07:00
mrg	6c04166876	Update port data wmask tests	2020-06-15 06:05:05 -07:00
mrg	02352c35d7	Fix hard coded layer in wmask	2020-06-14 17:10:32 -07:00
mrg	52ee7b0a19	Disable perimeter pins and make an option	2020-06-14 16:44:10 -07:00
mrg	78be9f367a	Add brain-dead router pins to perimeter	2020-06-14 15:52:09 -07:00
mrg	9930b5f3f6	Do not run tapless unit tests	2020-06-14 14:18:25 -07:00
mrg	7dc33285a7	Add contact to gate design rule to max for spacing inputs	2020-06-14 14:18:08 -07:00
mrg	8e8a97cc4b	Add correct boundary to SRAM	2020-06-14 14:17:35 -07:00
mrg	443c401561	pnand2 B input spaced from top	2020-06-14 14:17:04 -07:00
mrg	91f20f2cf6	Better centering of pinv_dec	2020-06-14 14:09:45 -07:00
mrg	8f1dc7eeea	Include mirror/rotate on translate_all boundary update	2020-06-13 06:50:53 -07:00
mrg	33a32101c9	DRC and LVS fixes for pinv_dec	2020-06-12 15:23:51 -07:00
mrg	443b8fbe23	Change s8 to sky130	2020-06-12 14:23:26 -07:00
mrg	54e4d147f6	Rail to ptx spacing based on routing layer not m1	2020-06-11 15:03:50 -07:00
mrg	e9780ea599	Add non-preferred directions for channel routes	2020-06-11 15:03:36 -07:00
mrg	8d52794c32	Remove printf in precharge	2020-06-11 11:57:52 -07:00
mrg	7ad2d54a69	Add pin and label purposes	2020-06-11 11:54:51 -07:00
mrg	1a2e0046b1	Add contact to gate spacing for precharge	2020-06-11 11:54:34 -07:00
mrg	089331ced3	Add stdc bounding box too	2020-06-11 11:54:16 -07:00
mrg	098219d56c	Add npc enclosure to poly contacts	2020-06-11 11:53:59 -07:00
mrg	f973dd6a5c	Save LVS model with no u too for Calibre	2020-06-11 11:53:34 -07:00
mrg	dff28a9997	Merge branch 'tech_migration' into dev	2020-06-10 17:09:05 -07:00
mrg	196e5998c8	Half poly space per cell at top and bottom.	2020-06-10 16:52:51 -07:00
mrg	fdf92d0da1	Rename test 14	2020-06-10 16:41:26 -07:00
mrg	0b4b5e7133	More exact input spacing in pnand3	2020-06-10 16:19:24 -07:00
mrg	bfd1abc79f	Replica column pins start at 0 height.	2020-06-10 14:58:55 -07:00
mrg	469cd260b9	Change bitcell array name to match	2020-06-10 14:54:20 -07:00
mrg	f2c45a230e	Add new replica column test. Add more skip tests.	2020-06-10 11:00:00 -07:00
mrg	10be2d08b5	Full path to skip tests file	2020-06-10 10:23:05 -07:00
mrg	5e3332453b	Allow power pins to start on any layer besides m1	2020-06-10 10:15:23 -07:00
mrg	c119e60e79	Add more s8 skip tests	2020-06-10 10:14:52 -07:00
mrg	d4fc88124a	Rename dff_buf test	2020-06-09 17:18:19 -07:00
mrg	064fe34edf	Fix pinvbuf layers	2020-06-09 17:16:35 -07:00
mrg	14782914b3	Remove vertical pand gates	2020-06-09 16:40:59 -07:00
mrg	e6babc301d	Incrase space for pnand gates	2020-06-09 16:34:15 -07:00
mrg	c6b875146d	Use local skip file	2020-06-09 16:33:59 -07:00
mrg	fd49d3ed6a	Add tech specific skip tests for making new techs.	2020-06-09 16:09:15 -07:00
mrg	580b0601b5	Unskip 20_psram_1bank_4mux_1rw_1r_test	2020-06-09 16:04:39 -07:00
mrg	a28e747a02	Fix precharge offset. Move well rules to design class.	2020-06-09 15:28:50 -07:00
mrg	148521c458	Remove stdc layer	2020-06-09 13:48:47 -07:00
mrg	157926960b	Flip freepdk45 flop, dff_buf route layer change	2020-06-09 13:48:16 -07:00
mrg	8c6d5b49be	Consider diffusion spacing in active offset	2020-06-09 13:09:52 -07:00
mrg	77fb7017c4	Merge branch 'tech_migration' into dev	2020-06-08 12:54:41 -07:00
mrg	9cc36c6d3a	Bus code converted to pins. Fix layers on control signal routes in bank.	2020-06-08 11:01:14 -07:00
Aditi Sinha	c39c0efd39	Updated spare col tests	2020-06-08 16:38:18 +00:00
Aditi Sinha	300522a1a8	Change spare enable pins offset to lower right	2020-06-08 14:31:46 +00:00
Aditi Sinha	ef940e0dc5	Fixes for functional test of spare cols	2020-06-08 05:02:04 +00:00
Aditi Sinha	d5041afebc	Merge branch 'dev' into bisr	2020-06-07 16:27:25 +00:00