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base
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Variable zjog. 512 port address test. s8 port address working.
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2020-06-04 16:01:32 -07:00 |
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bitcells
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merge conflict - port data
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2020-06-02 14:15:39 -07:00 |
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characterizer
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Fixes for functional test of spare cols
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2020-06-08 05:02:04 +00:00 |
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custom
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Hard cells can accept height parameter too.
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2020-06-01 16:46:00 -07:00 |
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datasheet
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Convert capital names to lower case for consistency
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2019-08-21 13:45:34 -07:00 |
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drc
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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example_configs
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revert example scn4m to non netlist only
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2020-02-09 23:52:11 -08:00 |
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gdsMill
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added purposes to addText(), removed reference to specific tech from gdsMill
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2020-02-19 16:26:52 -08:00 |
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modules
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Change spare enable pins offset to lower right
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2020-06-08 14:31:46 +00:00 |
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pgates
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Merge branch 'dev' into discrete_models
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2020-06-05 16:47:01 -07:00 |
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router
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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sram
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Merge branch 'dev' into bisr
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2020-06-07 16:27:25 +00:00 |
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tests
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Updated spare col tests
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2020-06-08 16:38:18 +00:00 |
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verify
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Don't force check in lib characterization. PEP8 formatting.
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2020-04-02 12:52:42 -07:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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Add layer-purpose GDS support. Various PEP8 fixes.
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2019-11-14 18:17:20 +00:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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Merge branch 'dev' into bisr
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2020-06-07 16:27:25 +00:00 |
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openram.py
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Characterization for extra rows
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2020-02-20 17:01:52 +00:00 |
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options.py
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Merge branch 'dev' into bisr
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2020-06-07 16:27:25 +00:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
c39c0efd39