Aditi Sinha 300522a1a8 Change spare enable pins offset to lower right

2020-06-08 14:31:46 +00:00

..

base

Variable zjog. 512 port address test. s8 port address working.

2020-06-04 16:01:32 -07:00

bitcells

merge conflict - port data

2020-06-02 14:15:39 -07:00

characterizer

Fixes for functional test of spare cols

2020-06-08 05:02:04 +00:00

custom

Hard cells can accept height parameter too.

2020-06-01 16:46:00 -07:00

datasheet

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drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

revert example scn4m to non netlist only

2020-02-09 23:52:11 -08:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Change spare enable pins offset to lower right

2020-06-08 14:31:46 +00:00

pgates

Merge branch 'dev' into discrete_models

2020-06-05 16:47:01 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

tests

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

verify

Don't force check in lib characterization. PEP8 formatting.

2020-04-02 12:52:42 -07:00

debug.py

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gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

Makefile

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openram.py

Characterization for extra rows

2020-02-20 17:01:52 +00:00

options.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

run_profile.sh

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sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

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