mrg 7ad2d54a69 Add pin and label purposes

2020-06-11 11:54:51 -07:00

..

base

Add pin and label purposes

2020-06-11 11:54:51 -07:00

bitcells

merge conflict - port data

2020-06-02 14:15:39 -07:00

characterizer

Fixes for functional test of spare cols

2020-06-08 05:02:04 +00:00

custom

Hard cells can accept height parameter too.

2020-06-01 16:46:00 -07:00

datasheet

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

revert example scn4m to non netlist only

2020-02-09 23:52:11 -08:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Merge branch 'tech_migration' into dev

2020-06-10 17:09:05 -07:00

pgates

Add contact to gate spacing for precharge

2020-06-11 11:54:34 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

tests

Merge branch 'tech_migration' into dev

2020-06-10 17:09:05 -07:00

verify

Don't force check in lib characterization. PEP8 formatting.

2020-04-02 12:52:42 -07:00

debug.py

Add layer-purpose GDS support. Various PEP8 fixes.

2019-11-14 18:17:20 +00:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Characterization for extra rows

2020-02-20 17:01:52 +00:00

options.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00