mrg f2c45a230e Add new replica column test. Add more skip tests.

2020-06-10 11:00:00 -07:00

..

base

Allow power pins to start on any layer besides m1

2020-06-10 10:15:23 -07:00

bitcells

merge conflict - port data

2020-06-02 14:15:39 -07:00

characterizer

Merge remote-tracking branch 'public/dev' into dev

2020-04-22 09:28:25 -07:00

custom

Hard cells can accept height parameter too.

2020-06-01 16:46:00 -07:00

datasheet

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

revert example scn4m to non netlist only

2020-02-09 23:52:11 -08:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Flip freepdk45 flop, dff_buf route layer change

2020-06-09 13:48:16 -07:00

pgates

Fix pinvbuf layers

2020-06-09 17:16:35 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Change L shape of rbl route

2020-06-04 11:03:39 -07:00

tests

Add new replica column test. Add more skip tests.

2020-06-10 11:00:00 -07:00

verify

Don't force check in lib characterization. PEP8 formatting.

2020-04-02 12:52:42 -07:00

debug.py

Add layer-purpose GDS support. Various PEP8 fixes.

2019-11-14 18:17:20 +00:00

gen_stimulus.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00

globals.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

Makefile

…

openram.py

Only setup bitcell when running top-level OpenRAM

2019-11-26 13:54:37 -08:00

options.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

run_profile.sh

…

sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00