f6f48a7b27
Add support for VCU108 board and Virtex UltraScale
2024-11-12 23:51:55 +01:00
0fd653e353
xilinx: replaced reverseWord by configBitstreamParser::reverse_32
2024-11-09 11:26:45 +01:00
e75e15bb63
configBitstreamParser: added static method to switch bits for 32bits value
2024-11-09 11:26:02 +01:00
543be23d03
main,spiFlash,xilinx: fix warnings
2024-11-09 11:24:16 +01:00
7acd1f2014
Add Support for Altera Max II EPM240T100C5N Board
2024-10-16 08:53:21 -04:00
43fcc6ce2c
Add ID and spiOverJtag bitstream for Stratix V GS D5
2024-10-10 19:59:31 +02:00
406e99c93a
Add xc2c64a QFN48
2024-10-01 13:45:44 -04:00
9c9ce07ad8
feat: adding support for the xc7z030
2024-09-26 17:41:49 +01:00
8e67d2ee04
arguments: fix read_dna and read_xadc typo
2024-09-25 07:24:15 +02:00
abb64a6aa1
spiFlash: added S25FL128S display register
2024-09-23 07:16:23 +02:00
b6963ad4a9
spiFlash: added MX25L enable/disable quad + display status register
2024-09-23 07:14:23 +02:00
faa1fc76fc
core,xilinx,device: added option/methods to enable/disable quad mode on SPI Flash
2024-09-23 07:09:30 +02:00
242357c46f
spiFlash: added method to enable/disable Quad mode support
2024-09-23 07:06:05 +02:00
924de0a13a
spiFlashdb: added quad support for S125FL
2024-09-23 07:00:56 +02:00
81422b6ca3
Merge pull request #481 from acceleratedtech/jwise/ti180-soj
...
efinix: add spiOverJtag support for Ti180J484
2024-08-31 08:20:04 +02:00
ffd32a61d2
Efinix: do not allow untested detect_flash() non-SoJ path until someone tries it out for sure
2024-08-29 18:08:57 -04:00
fca69cc702
spiFlash: added configuration/nonvolatile configuration register for spansion and micron SPI Flash
2024-08-25 09:34:14 +02:00
5d6daed815
spiFlashdb: added quad bit mask and corresponding register
2024-08-25 09:32:13 +02:00
755802afe1
spiFlashdb: added some flash's datasheet link
2024-08-25 09:31:13 +02:00
ad01d986c1
adding support for cyc5000
2024-08-24 21:32:00 -07:00
533b5b626a
spiFlashdb.hpp: reorder entries, reformat
2024-08-23 07:20:53 +02:00
90e62e07c3
efinix: add support for flash detect and flash dump in SoJ mode
2024-08-19 21:29:30 -04:00
5ec6eae63b
part.hpp: add Efinix Titanium Ti180
2024-08-07 19:24:52 -07:00
9edf1edb3f
board, doc: added KNJN Dragon-L PCI Express & HDMI FPGA board (Spartan6 xc6slx25tcsg324
2024-08-03 09:22:49 +02:00
0d657f0f65
spiFlashdb: added TI M25P80 (0x202014)
2024-08-03 09:22:02 +02:00
1d2b18aeaf
part: Xilinx spartan6 LX25T (xc6slx25T)
2024-08-01 08:47:19 +02:00
a509a28fa6
part.hpp: Xilinx spartan7 xc7s6 variant
2024-08-01 08:14:46 +02:00
768c6efcce
gowin: added detect_flash/erase_flash for gw2a FPGAs
2024-07-30 08:50:34 +02:00
a7cb7ec050
efinix: program(): thow exception when something fails
2024-07-29 07:54:38 +02:00
aed4f9a263
efinix: programJTAG return type void -> bool
2024-07-29 07:54:35 +02:00
bba3d9f3fb
efinix: programSPI return type void -> bool
2024-07-29 07:54:13 +02:00
a7a1a788ff
spiFlash: 0x0000 is not a valid jedec id
2024-07-29 07:45:45 +02:00
7e4b42b795
Adding support for AMD Virtex 7 FPGA VC709 Connectivity Kit Board
2024-07-12 23:32:14 -03:00
1042b6c269
Add xc7vx690t
2024-07-12 23:19:04 -03:00
58cc5033f0
spiFlash: removed unused variable ( #468 )
2024-07-06 08:51:28 +02:00
f6b6f6f9d8
spiFlash: added get_bp_mask to return default bp mask (unknown device) or compute mask based on bp_offset. Replace all manual mask compute. ( #468 )
2024-07-04 08:17:49 +02:00
e3f315a121
Add support for Numato Systems Mimas A7 board.
2024-06-22 08:03:14 -04:00
53530f7316
main: In help output, show how to detect flash
2024-06-20 16:25:41 +02:00
a341d1f441
add new device (Intel MAX10M40SCE144C8G) ( #461 )
...
* add 10M40SCE144
* change name
2024-06-13 15:09:32 +02:00
c468a69fc9
all devices / spiInterface / main: added method / infra to detect flash chip with --detect -f
2024-06-09 09:28:52 +02:00
d0dd71a28a
spiFlash: display_status_reg simplify again
2024-06-09 09:26:27 +02:00
36b1a7f9d9
spiFlash: read_id: display jedec ID. display_status_reg small fixes
2024-06-09 09:14:38 +02:00
3ba0012a2c
xilinx: added WBSTAR & BOOTSTS register read/decode. Fixed dec/hex format and padding
2024-06-04 08:45:51 +02:00
cb523199cc
spiFlash: enable_protection/disable_protection: uses mask to only deal by bp
2024-06-03 16:18:14 +02:00
2b80ce158b
spiFlash: added ask before writting TB when OTP, added missing write_enable and fixed mask
2024-06-03 15:23:12 +02:00
be188c0223
spiFlashdb.hpp: added IS25LP256D chip support
2024-06-03 11:27:51 +02:00
ed492715e1
xilinx: Add XADC reads of VCC registers
2024-05-23 09:40:19 -03:00
578c899327
../src/gwu2x_jtag.cpp
2024-05-22 20:54:14 +02:00
26b4516aeb
added lilygo-t-fpga board (based on gwu2x #434 )
2024-05-20 21:18:20 +02:00
53578876d5
added support for Gowin GWU2X USB (JTAG mode) ( #434 )
2024-05-20 21:10:29 +02:00
7e90d071d9
libusb_ll: rework. Splitted scan method -> help futur dev with a common code to detect/select usb devices
2024-05-20 16:18:50 +02:00
37a0f9c03e
device: fixed warning in read_registers
2024-05-20 16:16:42 +02:00
6e85edaa9a
adding support for XC2C64A-xVQ44 with ID 0x06e5e093 ( #458 )
...
* adding support for XC2C64A-xVQ44
* remove comment
2024-05-19 17:13:16 +02:00
66c47fe3bd
Add support for EP4CE6E22 and EP4CE10F17
2024-04-30 14:51:29 -04:00
55b094ce00
add EP4CGX150
2024-04-27 16:18:23 +07:00
943a458f03
src/part.hpp: Add xcau15p support.
2024-04-25 17:17:47 +02:00
4fe3d7ccc1
xilinx: added readback access to registers (stat, conf, ...)
2024-04-21 14:35:23 +02:00
99147efa27
board,doc: added CERN SPEC45 support
2024-03-28 22:15:17 +01:00
9b35959198
part: added xilinx xc6slx45t
2024-03-28 22:14:52 +01:00
172295fb38
spiFlashdb: added M25P32 chip
2024-03-28 22:12:57 +01:00
62f818cd68
Merge pull request #450 from kalata23/master
...
Added Zetta ZD25WQ16CSIGT
2024-03-28 22:02:21 +01:00
206795c9c7
Added Zetta ZD25WQ16CSIGT
2024-03-28 14:20:08 +02:00
089bc5aa4e
Add support for the Cyclone II
2024-03-27 12:58:50 -03:00
02c33271e0
lattice,xilinx: new try to fix (again) uint64_t print format
2024-03-18 06:57:59 +01:00
1d276ebb9d
spiFlashdb: MX25R6435F: added missing bp bit 4
2024-03-15 07:02:31 +01:00
41ecac5d0c
Merge pull request #447 from pu-cc/spiflashdb-mx25r643f
...
spiFlashdb: add MX25R6435F and fix SPIFlash::bp_to_len
2024-03-15 07:00:12 +01:00
972ded1298
spiFlashdb: add MX25R6435F and fix SPIFlash::bp_to_len
2024-03-15 00:44:17 +01:00
7dc3ff7803
gatemate: fix jtag-spi-bypass with dirtyJtag
2024-03-15 00:13:12 +01:00
e52d647d7b
gatemate: fix passive spi segfaults and improve verbosity
2024-03-15 00:11:11 +01:00
5bb8ce83b3
gatemate: fix CFG_MD typos
2024-03-15 00:07:05 +01:00
2e5c35edde
gatemate: remove flash reset, power_up and read_id duplicates
2024-03-14 23:31:34 +01:00
1304f67f1b
gatemate: fix unintended gpio access with dirtyJtag cables
2024-03-14 18:02:50 +01:00
f1bf4fdf57
jtag,main,xilinx: fix warnings, lint
2024-03-09 10:21:21 +01:00
6366518ff7
device,ftdiJtagMPSSE,jtag: check/lint happy
2024-03-07 06:58:31 +01:00
6dc2e752f4
ch347jtag: drop unused sync_cb
2024-03-07 06:57:27 +01:00
e299061992
xilinx.cpp: After programming, go to bypass
...
Needed for xc7s50 on VMM3 boards to detect FLASH
2024-03-04 15:33:25 +01:00
bcbd8aa0e3
new board: olimex_gatemateevb Olimex GateMate A1 EVB
2024-03-03 08:25:55 +01:00
645471a16c
spiFlashdb.hpp: Detect N25Q256A.
2024-03-01 13:38:23 +01:00
f57abf9024
Add Trenz TEC0330 board.
2024-03-01 13:38:12 +01:00
88c4d86e63
Add xc7vx330t
2024-03-01 10:50:28 +01:00
ae39b2c556
board.hpp: Add TE0712-8 Board (XC7A200TFBG484)
2024-02-28 22:46:01 +01:00
a2d8bc861f
Merge pull request #437 from UweBonnes/xc6v
...
Add spilOverJtag for Virtex6
2024-02-28 22:03:53 +01:00
4af0bf6ed5
update CH347 ( #424 )
2024-02-28 20:44:49 +01:00
a926ab9b88
Add (Cern) VMM3 board
2024-02-28 11:50:10 +01:00
0e99360d1c
Add (Cern) VEC_V6 Board
2024-02-28 11:50:10 +01:00
354d3f86ab
Virtex6: Add spiOverJtag for Virtex6, detect xc6vlx130 and provide bitfile for xc6vlx130tff784
2024-02-28 11:50:10 +01:00
956d9355a6
Add S25FL128L flash
2024-02-28 11:50:10 +01:00
85d9ca5d20
board: added digilent cmoda7_15t
2024-02-26 21:18:33 +01:00
0182d592be
dfu,ftdipp_mpsse: sprintf -> snprintf
2024-02-20 20:59:13 +01:00
3165552994
DFU: fix code to accept tinyDFU implementation (where not altsettings have an DFU descriptor)
2024-02-15 06:45:13 +01:00
ffc519c0e2
lattice: improve info about "BSE Error Code" from Device Status Register
2024-02-13 09:32:30 +01:00
e923ef4059
lattice nexus boards: change from CABLE_DEFAULT (i.e. 6MHz) to CABLE_MHZ(1) (i.e. 1MHz)
...
as at 6MHz the download of bitstreams is not stable.
With "not stable" we mean that:
- when dealing with Certus/Crosslink, most of the times it works
- when dealing with CertusPro devices, most of the times it doesn't work
We think this is due to the size of the bitstream and the way that the
transmission/storing is handled on the receiving side (i.e. the FPGA).
2024-02-13 09:24:47 +01:00
0f9422f09a
latticeBitParser: add support for loading Lattice (Nexus) encrypted bitstreams,
...
by adding key and preamble of encrypted bitstreams to if statements.
2024-02-13 09:22:34 +01:00
daa1e38799
xvc client: handle failed ll_write()
...
Avoids "Send instruction failed" in a tight loop...
2024-02-11 14:25:00 -08:00
4c737b2b96
xvc client ensure send() entire buffer
2024-02-11 14:25:00 -08:00
39be00fd56
Merge pull request #427 from jgroman/master
...
Fix Tang Primer 25K SRAM loading when flash is erased
2024-02-02 13:09:45 +01:00
eba9c37027
Fix SRAM loading on invalid flash
2024-02-02 12:54:17 +01:00
fc58ffed38
Update spiFlashdb.hpp for Macronix MX25L3233F used on Cmod A7-35T
...
Digilent changed from Micron N25Q032A to Macronix MX25L3233F in 2020/2021, so this flash is needed in openfpgaloader to load to Cmod A7-35T
2024-02-01 19:48:21 +01:00
f9c1aa4eed
Merge pull request #423 from jgroman/master
...
Add faulty MPSEE cmd 8E workaround
2024-01-29 07:17:50 +01:00
33eaf58869
Add faulty MPSEE cmd 8E workaround
2024-01-27 13:02:46 +01:00
1aaa1b37ac
board: add Antmicro LPDDR4 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:29:12 +01:00
59f5759888
board: add Antmicro DDR5 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:25:07 +01:00
17939d587e
board: add Antmicro DDR4 Tester board
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:23:27 +01:00
308e47c5c0
Merge pull request #420 from sean-anderson-seco/xilinx-ids
...
xilinx: Add remaining ZynqMP IDs
2024-01-19 07:25:54 +01:00
da0f6f6f2a
xilinx: Add remaining ZynqMP IDs
...
The IDs were taken from UG1085 v2.2 table 1-2.
2024-01-18 14:50:23 -05:00
9943c3072a
lattice: Add all MachXO[23] part IDs
...
The version field is the only difference between many parts in the
MachXO[23] family, including between different families. Add the version
field to all parts, fixing detection of some MachXO3 parts as MachXO2s.
The id codes were extracted from the BSDL files on Lattice's website.
2024-01-18 13:48:50 -05:00
4148be3d31
part: 0x012bc043 is for LCMXO2-4000HC
...
I found this when I was trying to program a LCMXO2-4000HC, but
openFPGALoader said it is a LCMX03LF-4300C:
$ openFPGALoader --detect
No cable or board specified: using direct ft2232 interface
Jtag frequency : requested 6.00MHz -> real 6.00MHz
index 0:
idcode 0x12bc043
manufacturer lattice
family MachXO3LF
model LCMX03LF-4300C
irlength 8
From what I found on the internet, the idcode for LCMX03LF-4300C seems
to be 0x612BC043:
https://bsdl.info/details.htm?sid=b483da5dec63d6cd88ca59b002289d77
2024-01-11 10:00:02 +08:00
a3826614b3
gowin: writeFLASH: increase delay before CRC check (required for 9K device)
2024-01-09 19:56:53 +01:00
0b59efcb42
src/gowin: GW5A/SPI flash: adding delay after erase flash and after SPI mode instruction. Seems fixed write error.
2024-01-09 18:48:21 +01:00
62ad3a3003
gowin: fix flash erase for GW1NSR-4C: during shiftDR sequence TDI MUST be 0x0000
2024-01-04 07:24:02 +01:00
c51dbcb0ed
Merge pull request #410 from pu-cc/gatemate-chain-fix
...
gatemate: fix configuration byte alignment in jtag chains
2023-12-27 14:42:29 +01:00
001f20c884
gatemate: use more suitable change to RUN_TEST_IDLE state
2023-12-27 13:38:13 +01:00
8c6c0ee85a
Add WebAssembly support.
2023-12-22 21:07:33 +00:00
bca3bd6623
Use correct format specifier for printing uint64_t.
2023-12-22 21:07:23 +00:00
cd40de37cb
main: allows mcufw only mode for gowin
2023-12-14 13:13:48 +01:00
22f33618b0
gowin: mcufw may be written without fs (but this erase all memory)
2023-12-14 13:13:29 +01:00
2093ce7520
gowin: fix gw1n external flash access
2023-12-14 11:48:14 +01:00
1dbc9e664b
gowin: programFlash/writeFlash: disable previous rewrite (fix write with tangnano4k)
2023-12-14 11:38:34 +01:00
1dfdec6ce1
gatemate: fix configuration in jtag chains
2023-12-12 10:21:30 +01:00
ed547ed893
boards: adding AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit
2023-12-11 12:23:37 +01:00
d8186c5e8a
gowin: GW5AST work around
2023-12-11 07:20:37 +01:00
1c7a4afd01
ftdipp_mpsse: display/typo
2023-12-11 07:18:02 +01:00
bd917d51ef
gowin: try second eraseSRAM before writeSRAM. Not always working but better...
2023-12-10 08:14:06 +01:00
b70a3991cc
Add pynq-z1 board
2023-12-08 14:51:38 -05:00
2a2435ecbe
board: Xilinx KCU105 (Kintex Ultrascale xcku040)
2023-12-08 16:00:59 +01:00
807d794703
latticeBitParser: add ECP3 VERIFY ID support (avoid to fail with bitstream)
2023-12-08 07:07:35 +01:00
fb587e73d8
gowin: Fix clk cycle after sending a command, don't read status register programSRAM sequence
2023-12-04 07:25:43 +01:00
0dcd851187
gowin: avoid multiple status register access
2023-12-04 07:05:40 +01:00
01d6244a0f
gowin: Fix status register parse for GW5AST
2023-12-04 07:01:56 +01:00
8007ffe263
xilinx: lint more happy
2023-11-25 15:14:32 +01:00
234f7f5a35
XADC and DNA for Xilinx FPGA ( #407 )
...
* xilinx: add XADC and DNA args, see https://github.com/cfib/openFPGALoaderXADC/tree/XADC_3
parts: add xcku060
* doc: add xcku060
2023-11-25 08:47:24 +01:00
b119a955a6
gowin: GW5A SPI flash support
2023-11-19 13:29:15 +01:00
a5f2aa56c8
gowin: displayReadReg update. Now GW5A field are correctly displayed
2023-11-19 10:25:06 +01:00
31c89e21a3
gowin: detectFamily new function
2023-11-19 10:18:45 +01:00
1cbdee362d
jtag,main: fix warnings
2023-11-19 10:17:54 +01:00
7059c15960
Add user device list for non-fpga JTAG devices
2023-11-10 14:00:24 -07:00
63c1950f2f
Add xc7k70t and small fixes for xc7k160t
2023-11-09 07:45:46 +07:00
1a86fa21ae
Merge pull request #399 from bg-gsl/fix_lattice_bscan_nexus
...
Fix lattice bscan nexus in clearSRAM()
2023-11-08 12:47:34 +01:00
fa5ff873e4
lattice.cpp: restore bypass instruction in clearSRAM()
2023-11-08 09:49:14 +01:00
f71858f96a
Rewrite GOWIN algorithms
2023-10-29 08:07:48 +01:00
790d2bccab
fsParser: adding GW5A-25 IDCODE
2023-10-29 07:02:12 +01:00
59b56bcc95
all jtag cable: no more hardcoding tdi bit with writeTMS
2023-10-29 06:41:39 +01:00
43ae0d8fdd
ftdiJtagMPSSE,jtagInterface: {set|get}{Read|Write}Edge signature
2023-10-29 06:12:09 +01:00
46ce2e61a7
ALINX AX7101 board.
2023-10-28 17:22:42 +02:00
d58a1c3fc7
lattice: correct mask for sram erase for NEXUS_FAMILY, as it is 0x00
2023-10-26 11:30:24 +02:00
917e42127b
lattice: fix bscan register initialization inside clearSRAM()
...
For NEXUS family fpgas, the Bscan register is 362 bits long
or 45.25 bytes => 46 bytes.
This error was already correct when programming the sram.
clearSRAM() is instead used when programming the spi flash memory.
2023-10-25 17:43:49 +02:00
a87d689d83
ALINX AX7102 board.
2023-10-24 14:03:18 +02:00
fd8497026a
ftdiJtagMPSSE,jtag,jtagInterface: allows to force read/write edge configuration (useful to mimic SPI through JTAG)
2023-10-24 07:26:19 +02:00
b76a67963e
board: SiPEED tang Mega 138K
2023-10-24 06:11:53 +02:00
9a2fe6e157
board: SiPEED tang Primer 25K
2023-10-24 06:07:42 +02:00
988bedefb6
lattice: fix typo / warning
2023-10-23 07:12:45 +02:00
590611a8d5
lattice: fix the warning "left shift count >= width of type" shown in win32/64 builds
2023-10-20 08:44:20 +02:00
bab386911a
spi flash: add mapping for Micron MT25/N25Q128_1_8V (Lattice Certus Versa and CertusPro eval boards) and distinguish between N25Q128 1.8V and 3V memories
2023-10-20 07:57:56 +02:00
940da5fb2b
spi flash: add mapping for Macronix MX25L51245G (CertusPro Versa board and gr740-mini)
2023-10-20 07:55:53 +02:00
5f6074a7fc
lattice: fix bscan width and other minor things for NEXUS family
2023-10-20 07:55:53 +02:00
dce0c050a7
board: add gr740-mini
2023-10-20 07:55:53 +02:00
2754e99215
cable: add FTDI FT4232HP mapping
2023-10-20 07:55:53 +02:00
0bbf817c92
part: fix typo
2023-10-19 17:46:50 +02:00
32ef0bd29c
Adding xcku115 to parts list ( #394 )
...
* Adding xcku115 to parts list
* Adding xcku115 to list of supported FPGAs
---------
Co-authored-by: Stephen Goadhouse <stephen.david.goadhouse@cern.ch>
2023-10-19 17:45:42 +02:00
dafe350fbe
lattice nexus family: REFRESH (plus config logic reset) in case of fpga in error state and add capabilities to handle the whole 64-bits status register
2023-10-12 09:06:54 +02:00
5733ca29c3
fix lattice programming and add nexus boards
...
Fix to lattice programming:
we considered a svf file generated by Lattice Radiant-Programmer
and compared it with the current way lattice devices were programmed.
There were few differences dealing with configuration reset and REFRESH.
These fixes allow us to program an fpga when it is in a state
of error (e.g. there's no bitstream in the SPI Flash).
Lattice parts added:
- CertusPro FPGA
Nexus boards added:
- Certus Versa Evaluation board
- CertusPro Evaluation board
- CertusPro Versa Evaluation board
2023-10-11 09:52:45 +02:00
ec35f15a51
altera,efinix,gowin,xilinx: Fix 'Flash SRAM' -> 'Load SRAM'
2023-10-09 14:53:57 +02:00
18056180a8
gatemate: do not call ftdi-related routines when using alternative cables
2023-10-04 15:41:10 +02:00
ad5ada90db
board: trion_t20_bga256_jtag support
2023-10-03 06:51:38 +02:00
e9b31425d6
cable: efinix jtag ft2232 variant
2023-10-03 06:48:47 +02:00
c0ad3225cc
Add support for Xilinx xczu17eg. It's tested on xczu17eg board with Digilent HS3 at 30Mbps.
2023-09-22 19:33:01 -07:00
c82a8e6207
Make CH347 driver faster
...
Speed up toggleClk
Defer write-only USB transactions to better utilize bus
2023-09-22 07:08:48 +02:00
67159e8297
Move JTAG chain bit init to device_select()
2023-09-22 07:05:20 +02:00
4c39abf51c
Add missing pieces to JTAG
2023-09-22 07:01:48 +02:00
85f9791600
drop div_by_5 to allow 2.5MHz clock
2023-09-22 06:55:21 +02:00
01ac90a172
[xilinx] add jtag->flush before sleep
2023-09-21 07:38:25 +02:00
b10be9ae8a
properly fill dummy arrays
2023-09-21 07:36:41 +02:00
d3410e0e30
Update JTAG chain detect
2023-09-21 07:33:54 +02:00
afbf0c4ff8
board: adding @lambdaconcept ecpix5_r03 (ft4232)
2023-09-21 06:24:30 +02:00
6c16417ee9
Merge UPDATE_DR and UPDATE_IR handling in JTAG state machines
2023-09-20 07:59:34 +02:00
6a0de15bff
Parse LoadingRate field
2023-09-20 07:58:06 +02:00
0c89ac9a44
Add GD32VF103 to misc devices
2023-09-20 07:48:21 +02:00
94b62460c5
jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' ( fix #189 and #133
2023-09-17 08:59:26 +02:00
9810735e32
jtag: rework detectChain: try unmasked idcode first
2023-09-14 21:53:27 +02:00
57fc9bcb6f
part: machXO3: re-add partially revision
2023-09-14 21:52:53 +02:00
5e9cc7c440
pass along reset paramaters to provide control to the caller
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Upsteam-Status: Submitted [https://github.com/traucucayre/openFPGALoader ]
- Submitted to upstream, waiting approval
2023-09-10 20:46:08 -07:00
c417ce6746
lattice: spi_put: avoid loop when tx == NULL
2023-09-06 15:50:28 +02:00
61b59ce827
jtag: fix state machine (issue introduce by commit 9e91c3)
2023-09-06 15:47:32 +02:00
9e91c31e31
Fixes for PVS errors
2023-09-01 22:30:24 +03:00
0f3afbcaea
Make IDCODE unsigned
2023-08-29 20:01:21 +03:00
8976404b78
Use JTAG state
2023-08-29 20:00:28 +03:00
1908ccd83b
make output buffer const
2023-08-29 19:51:41 +03:00
0de2ea6b39
gowin: add preliminary support for GW5AST-138
...
Arora V series is a new series of Gowin FPGA, in which the flashing
process has changed.
Add preliminary support by adding FS file line count and deal with the
SRAM writing process. Flash writing is not yet done.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-12 12:36:06 +08:00
6a4e107e42
part: add known ID codes for GW5 series
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Codes are from Gowin UG704.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-09 22:11:41 +08:00
9d22d62a54
part/board: adding Avnet Mini-ITX
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Adding the Avnet Mini-ITX dev board that uses the XC7Z100 Zynq-7000
device.
2023-08-07 17:06:02 +01:00
e3c8d6be1d
board: added QMTECH cyclone10 LP starter kit (10CL016YU484C8G)
2023-08-05 11:49:53 +02:00
7424ea2af9
part: update altera/intel idcode (same idcode for III/IV/10 LP)
2023-08-05 06:47:51 +02:00
baff0cad1e
src/part: Fix Xilinx XC2 ident.
2023-08-03 16:12:51 +02:00
502f38fb00
src/part.hpp: Add Kintex Ultrascale+ KU3P ID-Code.
2023-08-03 16:07:55 +02:00
4042646434
src/part.hpp: Add separator for each vendor.
2023-08-03 16:07:43 +02:00
c3e0707f6b
src/part.hpp: Reorder families (older first, smaller first) and minor alignment cleanups.
2023-08-03 16:07:33 +02:00
a1dea79230
src/part.hpp: Add separator for each chip family.
2023-08-03 16:07:24 +02:00
4c5f6f361b
svf_jtag: fix -Wmismatched-new-delete delete -> delete[]
2023-08-03 07:53:59 +02:00
6ef87c5466
ftdipp_mpsse: fix format-zero-length snprintf -> memset
2023-08-03 07:43:56 +02:00
0e1e07262c
ftdispi: add missing status_pin
2023-08-03 07:42:06 +02:00
Nicolas Schodet
Gwenhael Goavec-Merou
sab
Andreas Galauner
Miguel Flores-Acton
Shareef Jalloq
bma
Joshua Wise
Greg Steiert
Julio Nunes Avelar
Stéphane Potvin
Uwe Bonnes
Christoph Metzner
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Colin O'Flynn
Michael Schenk
Evan Kahn
Hans Baier
Florent Kermarrec
kalata23
uint69-t
Gwenhael Goavec-Merou
Patrick Urban
ZhiYuanNJ
Gwenhael Goavec
Giovanni Bruni
Michael Davidsaver
jgroman
sigmaeo
Michal Sieron
Sean Anderson
Chuang Zhu
Catherine
Tim Paine
bma
Mark Featherston
Hans Baier
Alexey Starikovskiy
Haakan T Johansson
sgoadhouse
Zhongyi Chen
Rodrigo Rengifo
Icenowy Zheng
Shareef Jalloq