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openFPGALoader
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jtag: shiftDR: (fix daisy chain) when more than one FPGA, a sequence of '0' before and/or after must be sent instead of '1' (fix #189 and #133

This commit is contained in:
Gwenhael Goavec-Merou 2023-09-17 08:59:26 +02:00
parent 9810735e32
commit 94b62460c5
1 changed files with 2 additions and 2 deletions
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4
src/jtag.cpp
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@ -345,7 +345,7 @@ int Jtag::shiftDR(const uint8_t *tdi, unsigned char *tdo, int drlen, tapState_t
if (bits_before > 0) {
int n = (bits_before + 7) / 8;
uint8_t tx[n];
memset(tx, 0xff, n);
memset(tx, 0x00, n);
read_write(tx, NULL, bits_before, 0);
}
}
@ -363,7 +363,7 @@ int Jtag::shiftDR(const uint8_t *tdi, unsigned char *tdo, int drlen, tapState_t
if (bits_after > 0) {
int n = (bits_after + 7) / 8;
uint8_t tx[n];
memset(tx, 0xff, n);
memset(tx, 0x00, n);
read_write(tx, NULL, bits_after, 1); // its the last force
// tms high with last bit
}