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board: add Antmicro LPDDR4 Tester board

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Signed-off-by: Michal Sieron <[email protected]>
This commit is contained in:
Michal Sieron
2024-01-25 12:29:12 +01:00
committed by Tomasz Michalak
parent 59f5759888
commit 1aaa1b37ac
2 changed files with 8 additions and 0 deletions
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doc/boards.yml
+7
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@@ -76,6 +76,13 @@
Memory: OK
Flash: OK
- ID: antmicro_lpddr4_tester
Description: Antmicro LPDDR4 Test Board
URL: https://opensource.antmicro.com/projects/lpddr4-test-board
FPGA: Kintex7 xc7k70t
Memory: OK
Flash: OK
- ID: arty_a7_35t
Description: Digilent Arty A7
URL: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start
src/board.hpp
+1
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@@ -113,6 +113,7 @@ static std::map <std::string, target_board_t> board_list = {
JTAG_BOARD("alinx_ax7102", "xc7a100tfgg484", "", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr4_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_ddr5_tester", "xc7k160tffg676", "ft4232", 0, 0, CABLE_DEFAULT),
JTAG_BOARD("antmicro_lpddr4_tester", "xc7k70tfbg484", "ft4232", 0, 0, CABLE_DEFAULT),
/* left for backward compatibility, use right name instead */
JTAG_BOARD("arty", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),
JTAG_BOARD("arty_a7_35t", "xc7a35tcsg324", "digilent", 0, 0, CABLE_MHZ(10)),