Add support for EP4CE6E22 and EP4CE10F17

spiOverJtag/Makefile

@@ -21,7 +21,7 @@ XILINX_PARTS := xc3s500evq100 \
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
 
 ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
-	ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce223 5ce423 5ce523 5ce927
+	ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce223 5ce423 5ce523 5ce927
 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
 
 BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)

spiOverJtag/build.py

@@ -179,6 +179,8 @@ else:
         "ep4ce11523" : "EP4CE115F23C7",
         "ep4ce2217"  : "EP4CE22F17C6",
         "ep4ce1523"  : "EP4CE15F23C8",
+        "ep4ce1017"  : "EP4CE10F17C8",
+        "ep4ce622"   : "EP4CE6E22C8",
         "5ce223"     : "5CEFA2F23I7",
         "5ce523"     : "5CEFA5F23I7",
         "5ce423"     : "5CEBA4F23C8",

src/part.hpp

@@ -168,6 +168,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 
 	/* Altera Cyclone II/III/IV/10 LP */
         {0x020b10dd, {"altera", "cyclone II", "EP2C5", 10}},
+	{0x020f10dd, {"altera", "cyclone III/IV/10 LP", "EP4CE6/EP4CE10",           10}},
 	{0x020f20dd, {"altera", "cyclone III/IV/10 LP", "EP3C16/EP4CE15/10CL016",   10}},
 	{0x020f70dd, {"altera", "cyclone III/IV/10 LP", "EP3C120/EP4CE115/10CL120", 10}},
 	{0x028040dd, {"altera", "cyclone IV GX", "EP4CGX150", 10}},