fix lattice programming and add nexus boards
Fix to lattice programming: we considered a svf file generated by Lattice Radiant-Programmer and compared it with the current way lattice devices were programmed. There were few differences dealing with configuration reset and REFRESH. These fixes allow us to program an fpga when it is in a state of error (e.g. there's no bitstream in the SPI Flash). Lattice parts added: - CertusPro FPGA Nexus boards added: - Certus Versa Evaluation board - CertusPro Evaluation board - CertusPro Versa Evaluation board
This commit is contained in:
Giovanni Bruni
parent
ec35f15a51
commit
5733ca29c3
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@ -126,7 +126,10 @@ static std::map <std::string, target_board_t> board_list = {
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JTAG_BOARD("colorlight-i5", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("colorlight-i9", "", "cmsisdap", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("colorlight-i9+", "xc7a50tfgg484", "", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("crosslinknx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("certusnx_versa_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("certuspronx_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("certuspronx_versa_evn", "", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("cyc1000", "10cl025256", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("c10lp-refkit", "10cl055484", "ft2232", 0, 0, CABLE_DEFAULT),
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JTAG_BOARD("de0", "", "usb-blaster",0, 0, CABLE_DEFAULT),
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@ -28,7 +28,7 @@ using namespace std;
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#define ISC_ENABLE 0xC6 /* ISC_ENABLE - Offline Mode */
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# define ISC_ENABLE_FLASH_MODE (1 << 3)
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# define ISC_ENABLE_SRAM_MODE (0 << 3)
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#define ISC_ENABLE_TRANSPARANT 0x74 /* This command is used to put the device in transparent mode */
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#define ISC_ENABLE_TRANSPARENT 0x74 /* ISC_ENABLE_X This command is used to put the device in transparent mode */
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#define ISC_DISABLE 0x26 /* ISC_DISABLE */
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#define READ_DEVICE_ID_CODE 0xE0 /* IDCODE_PUB */
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#define FLASH_ERASE 0x0E /* ISC_ERASE */
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@ -133,6 +133,7 @@ using namespace std;
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#define PROG_ECDSA_PUBKEY3 0x63 /* This command is used to program the fourth 128 bits of the ECDSA Public Key. */
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#define READ_ECDSA_PUBKEY3 0x64 /* This command is used to read the fourth 128 bits of the ECDSA Public Key. */
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#define ISC_NOOP 0xff /* This command is no operation command (NOOP) or null operation. */
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#define LSC_DEVICE_CONTROL 0x7D /* Multiple commands. Bit 3: configuration reset */
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#define PUBKEY_LENGTH_BYTES 64 /* length of the public key (MachXO3D) in bytes */
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@ -204,6 +205,8 @@ Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
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_fpga_family = NEXUS_FAMILY;
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} else if (family == "CertusNX") {
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_fpga_family = NEXUS_FAMILY;
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} else if (family == "CertusProNX") {
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_fpga_family = NEXUS_FAMILY;
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} else {
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printError("Unknown device family");
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throw std::exception();
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@ -303,7 +306,17 @@ bool Lattice::program_mem()
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memset(tx_buf, 0xff, 26);
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wr_rd(0x1C, tx_buf, 26, NULL, 0);
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wr_rd(0xFf, NULL, 0, NULL, 0);
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/* SRAM TRANSPARENT mode ISC_ENABLE_X 0x74 */
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uint8_t tx_tmp[1] = {0x00};
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// wr_rd(ISC_ENABLE_TRANSPARENT, tx_tmp, 1, NULL, 0);
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// _jtag->set_state(Jtag::RUN_TEST_IDLE);
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// _jtag->toggleClk(1000);
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/* LSC_REFRESH 0x79 -- "Equivalent to toggle PROGRAMN pin" */
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wr_rd(REFRESH, NULL, 0, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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sleep(5);
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/* ISC Enable 0xC6 */
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printInfo("Enable configuration: ", false);
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@ -315,6 +328,25 @@ bool Lattice::program_mem()
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printSuccess("DONE");
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}
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/* LSC_DEVICE_CONTROL 0x7D -- configuration reset */
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tx_tmp[0] = 0x08;
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wr_rd(LSC_DEVICE_CONTROL, tx_tmp, 1, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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if(!pollBusyFlag()) {
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printError("FAIL");
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return false;
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}
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tx_tmp[0] = 0x00;
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wr_rd(LSC_DEVICE_CONTROL, tx_tmp, 1, NULL, 0);
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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if(!pollBusyFlag()) {
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printError("FAIL");
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return false;
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}
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/* ISC ERASE */
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printInfo("SRAM erase: ", false);
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if (flashErase(FLASH_ERASE_SRAM) == false) {
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@ -356,6 +388,9 @@ bool Lattice::program_mem()
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_jtag->shiftDR(tmp, NULL, size*8, next_state);
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}
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_jtag->set_state(Jtag::RUN_TEST_IDLE);
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_jtag->toggleClk(1000);
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uint32_t status_mask;
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if (_fpga_family == MACHXO3D_FAMILY)
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status_mask = REG_STATUS_MACHXO3D_CNF_CHK_MASK;
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@ -1307,7 +1342,7 @@ uint16_t Lattice::getUFMStartPageFromJEDEC(JedParser *_jed, int id)
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addres.
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TODO: In any case, JEDEC files don't carry part information. Verify against
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IDCODE read previously? */
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if(raw_page_offset > 9211) {
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return raw_page_offset - 9211 - 1; // 7000
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} else if(raw_page_offset > 5758) {
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@ -212,6 +212,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
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{0x310F0043, {"lattice", "CertusNX", "LFD2NX-17", 8}},
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{0x310F1043, {"lattice", "CertusNX", "LFD2NX-40", 8}},
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/* Lattice CertusPro-NX */
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{0x010F4043, {"lattice", "CertusProNX", "LFCPNX-100", 8}},
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/**************************************************************************/
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/* Gowin */
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/**************************************************************************/
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