adding support for XC2C64A-xVQ44 with ID 0x06e5e093 (#458)

* adding support for XC2C64A-xVQ44

* remove comment

src/part.hpp

@@ -40,6 +40,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 
 	/* Xilinx XC2 */
 	{0x06e5d093, {"xilinx", "xc2c",     "xc2c64a",   8}},
+	{0x06e5e093, {"xilinx", "xc2c",     "xc2c64a",   8}},
 	{0x06e1c093, {"xilinx", "xc2c",     "xc2c32a",   8}},
 
 	/* Xilinx XC9 */

src/xilinx.cpp

@@ -1707,6 +1707,9 @@ void Xilinx::xc2c_init(uint32_t idcode)
 	_fpga_family = XC2C_FAMILY;
 	std::string model = fpga_list[idcode].model;
 	int underscore_pos = model.find_first_of('_', 0);
+	if (underscore_pos == model.npos) {
+		underscore_pos = model.length();
+	}
 	snprintf(_cpld_base_name, underscore_pos,
 			"%s", model.substr(0, underscore_pos).c_str());
 	switch ((idcode >> 16) & 0x3f) {

src/xilinx.hpp

@@ -233,7 +233,7 @@ class Xilinx: public Device, SPIInterface {
 		uint16_t _cpld_nb_row; /**< number of flash rows */
 		uint16_t _cpld_nb_col; /**< number of cols in a row */
 		uint16_t _cpld_addr_size; /**< number of addr bits */
-		char _cpld_base_name[7]; /**< cpld name (without package size) */
+		char _cpld_base_name[8]; /**< cpld name (without package size) */
 		int _irlen; /**< IR bit length */
 		std::map<std::string, std::vector<uint8_t>> _ircode_map; /**< bscan instructions based on model */
 		std::string _secondary_filename; /* path to the secondary flash file (SPIx8) */