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altera,efinix,gowin,xilinx: Fix 'Flash SRAM' -> 'Load SRAM'

This commit is contained in:
Gwenhael Goavec-Merou 2023-10-09 14:53:57 +02:00
parent 3e37a915bc
commit ec35f15a51
3 changed files with 4 additions and 4 deletions
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2
src/altera.cpp
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@ -97,7 +97,7 @@ void Altera::programMem(RawParser &_bit)
_jtag->set_state(Jtag::RUN_TEST_IDLE);
_jtag->toggleClk(1000000/clk_period);
/* write */
ProgressBar progress("Flash SRAM", byte_length, 50, _quiet);
ProgressBar progress("Load SRAM", byte_length, 50, _quiet);
int xfer_len = 512;
int tx_len;

2
src/gowin.cpp
View File

@ -636,7 +636,7 @@ bool Gowin::flashSRAM(const uint8_t *data, int length)
Jtag::tapState_t tx_end;
int byte_length = length / 8;
ProgressBar progress("Flash SRAM", byte_length, 50, _quiet);
ProgressBar progress("Load SRAM", byte_length, 50, _quiet);
/* UG704 3.4.3 */
if (is_gw5a) {

4
src/xilinx.cpp
View File

@ -577,7 +577,7 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile)
Jtag::tapState_t tx_end;
int burst_len = byte_length / 100;
ProgressBar progress("Flash SRAM", byte_length, 50, _quiet);
ProgressBar progress("Load SRAM", byte_length, 50, _quiet);
for (int i=0; i < byte_length; i+=burst_len) {
if (i + burst_len > byte_length) {
@ -733,7 +733,7 @@ bool Xilinx::xc3s_flow_program(ConfigBitstreamParser *bit)
const uint8_t *data = bit->getData();
int tx_len = burst_len * 8;
Jtag::tapState_t tx_end = Jtag::SHIFT_DR;
ProgressBar progress("Flash SRAM", byte_length, 50, _quiet);
ProgressBar progress("Load SRAM", byte_length, 50, _quiet);
flow_enable();