Add support for VCU108 board and Virtex UltraScale

doc/FPGAs.yml

@@ -290,6 +290,13 @@ Xilinx:
     Memory: OK
     Flash: OK
 
+  - Description: Virtex UltraScale
+    Model:
+      - xcvu095
+    URL: https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/virtex-ultrascale.html#productTable
+    Memory: OK
+    Flash: TBD
+
   - Description: Virtex UltraScale+
     Model:
       - xcvu9p

doc/boards.yml

@@ -867,6 +867,13 @@
   Memory: OK
   Flash: NA
 
+- ID: vcu108
+  Description: Xilinx VCU108
+  URL: https://www.xilinx.com/products/boards-and-kits/vcu108.html
+  FPGA: Virtex UltraScale xcvu095-ffva2104
+  Memory: OK
+  Flash: TBD
+
 - ID: vcu118
   Description: Xilinx VCU118
   URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html

src/board.hpp

@@ -236,6 +236,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("usrpx310",        "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
 	JTAG_BOARD("vec_v6",          "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vc709", 		  "xc7vx690tffg1761", "digilent", 0, 0, CABLE_MHZ(15)),
+	JTAG_BOARD("vcu108",          "xcvu095-ffva2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu118",          "xcvu9p-flga2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu128",          "xcvu37p-fsvh2892", "ft4232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu1525",         "xcvu9p-fsgd2104",  "ft4232", 0, 0, CABLE_MHZ(15)),

src/part.hpp

@@ -106,6 +106,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x13919093, {"xilinx", "kintexus", "xcku060", 6}},
 	{0x1390d093, {"xilinx", "kintexus", "xcku115", 6}},
 
+	/* Xilinx Ultrascale / Virtex */
+	{0x03842093, {"xilinx", "virtexus", "xcvu095", 6}},
+
 	/* Xilinx Ultrascale+ / Artix */
 	{0x04AC2093, {"xilinx", "artixusp", "xcau15p", 6}},
 	{0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}},

src/xilinx.cpp

@@ -356,6 +356,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = KINTEXUSP_FAMILY;
 	} else if (family == "artixusp") {
 		_fpga_family = ARTIXUSP_FAMILY;
+	} else if (family == "virtexus") {
+		_fpga_family = VIRTEXUS_FAMILY;
 	} else if (family == "virtexusp") {
 		_fpga_family = VIRTEXUSP_FAMILY;
 		_ircode_map = ircode_mapping.at("virtexusp");

src/xilinx.hpp

@@ -194,6 +194,7 @@ class Xilinx: public Device, SPIInterface {
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,
 			ARTIXUSP_FAMILY,
+			VIRTEXUS_FAMILY,
 			VIRTEXUSP_FAMILY,
 			UNKNOWN_FAMILY  = 999
 		};