lattice: fix bscan width and other minor things for NEXUS family
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dce0c050a7
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@ -103,7 +103,7 @@ using namespace std;
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# define REG_STATUS_AUTH_DONE (1 << 18) /* Authentication done */
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# define REG_STATUS_PRI_BOOT_FAIL (1 << 21) /* Primary boot failure (1= Fail) even though secondary boot successful */
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# define REG_STATUS_CNF_CHK_MASK (0x0f << 23) /* Configuration Status Check */
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#define REG_STATUS_PRV_CNF_CHK_MASK (0x0fUL << 33) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */
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#define REG_STATUS_PRV_CNF_CHK_MASK (0x0fUL << 34) /* NEXUS_FAMILY: Configuration Status Check of previous bitstrem */
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# define REG_STATUS_MACHXO3D_CNF_CHK_MASK (0x0f << 22) /* Configuration Status Check */
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# define REG_STATUS_EXEC_ERR (1 << 26) /*** NOT specified for MachXO3D ***/
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# define REG_STATUS_DEV_VERIFIED (1 << 27) /* I=0 Device verified correct, I=1 Device failed to verify */
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@ -301,11 +301,20 @@ bool Lattice::program_mem()
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displayReadReg(readStatusReg());
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}
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/* The command code 0x1C is not listed in the manual? */
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/* preload 0x1C */
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uint8_t tx_buf[26];
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memset(tx_buf, 0xff, 26);
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wr_rd(0x1C, tx_buf, 26, NULL, 0);
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/* The command code 0x1C is not listed in the manual?
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* PRELOAD/SAMPLE 0x1C
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* For NEXUS family fpgas, the Bscan register is 362 bits long or
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* 45.25 bytes => 46 bytes
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*/
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uint8_t tx_buf[46];
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memset(tx_buf, 0xff, 46);
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int tx_len;
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if(_fpga_family == NEXUS_FAMILY){
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tx_len = 46;
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} else {
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tx_len = 26;
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}
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wr_rd(0x1C, tx_buf, tx_len, NULL, 0);
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/* LSC_REFRESH 0x79 -- "Equivalent to toggle PROGRAMN pin"
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* We REFRESH only if the fpga is in a status of error due to
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@ -375,9 +384,15 @@ bool Lattice::program_mem()
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printSuccess("DONE");
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}
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/* ISC ERASE */
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/* ISC ERASE
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* For Nexus family (from svf file): 1 byte to tx 0x00
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*/
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printInfo("SRAM erase: ", false);
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if (flashErase(FLASH_ERASE_SRAM) == false) {
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uint32_t mask_erase[1] = {FLASH_ERASE_SRAM};
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if (_fpga_family == NEXUS_FAMILY){
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mask_erase[0] = 0x00;
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}
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if (flashErase(mask_erase[0]) == false) {
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printError("FAIL");
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displayReadReg(readStatusReg());
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return false;
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