Fischer Moseley
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28be273828
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uart: use wiring.Component for internal bus
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2026-02-12 02:09:17 -07:00 |
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Fischer Moseley
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31d11aff19
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uart: remove unused bridge testbenches
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2026-02-11 14:55:34 -07:00 |
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Fischer Moseley
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ccc102a0f8
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uart: fix tests for receiver and transmitter modules
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2026-02-11 14:54:26 -07:00 |
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Fischer Moseley
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c47b0df07b
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uart: update top-level wiring in UARTInterface
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2026-02-11 13:54:05 -07:00 |
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Fischer Moseley
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52b3474655
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uart: use wiring.Component instead of plain Elaborateable
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2026-02-10 20:54:29 -07:00 |
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Fischer Moseley
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62049bac84
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meta: replace Signal(1) with Signal()
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2026-01-19 16:31:12 -07:00 |
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Fischer Moseley
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614c3a5d7b
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uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
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2026-01-19 16:29:09 -07:00 |
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Fischer Moseley
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de6ce45f2e
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ethernet: remove obsolete tests, fix naming
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2026-01-19 16:26:33 -07:00 |
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Fischer Moseley
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23b7f53fe2
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ethernet: bugfix in read transmit logic
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2026-01-02 14:10:19 -07:00 |
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Fischer Moseley
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226d1afd9a
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ethernet: use new bridge in EthernetInterface
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2026-01-02 13:19:50 -07:00 |
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Fischer Moseley
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9611c0b554
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uart: fix #36, explicitly handle scientific notation in YAML config
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2025-04-06 18:28:29 -06:00 |
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Fischer Moseley
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f91f7c5fbb
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meta: add pre-commit, commit changes it makes
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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5759da568d
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tests: remove redundant test_toolchains test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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9937269c19
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ethernet: add individual methods for each flavor of MII
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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ccecc16726
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ethernet: fix path to divider.sv
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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da21a3a414
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ethernet: load divider.sv via symlink
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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363bef8d87
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ethernet: add HWITL ethernet test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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2761507803
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tests: add ethernet_io_core to build_examples test
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2024-11-27 19:10:52 -07:00 |
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Fischer Moseley
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cfbf372862
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uart: remove flaky nexys4ddr baudrate mismatch test case
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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d450221ed8
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tests: fix test_config_export
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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9d2ec45689
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uart: add stall_interval parameter and tests
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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cf62dd07bb
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logic_analyzer: default to immediate instead of single-shot, add intelligence to to_config()
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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2c124200da
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docs: autogenerate Python API docs, update IO core docs
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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1e7d4e92e7
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tests: fix bug where base_addr was not passed but not used
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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daedb91ff2
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meta: sort imports with ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b1caec9c57
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meta: switch from black to ruff
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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ecfbdaa86b
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cli: remove JSON loader, add test for instantiation generation
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b31a655d58
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tests: include building examples in test suite
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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3ba93efd2f
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meta: expose Amaranth API via __all__
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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0d15abe4d1
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ethernet: update __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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0bdfd9a5f7
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tests: fix mem_core_hw
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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165c6e46ca
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tests: fix logic_analyzer_sim
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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a01b6981e2
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tests: refactor to use Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b20d7c7822
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logic analyzer: move __init__ away from config dict
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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743f434652
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meta: add boilerplate for Amaranth-native API
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2024-10-08 11:42:10 -06:00 |
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Fischer Moseley
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b87f8cbc48
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meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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753a3f9427
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meta: finish moving simulations to new async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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8fd943257c
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sim: update testbenches to async API
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2024-07-17 18:51:05 -07:00 |
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Fischer Moseley
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13bc196a34
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rename Nexys A7 to Nexys 4 DDR
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2024-05-12 10:35:18 -07:00 |
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Fischer Moseley
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bd452d94a4
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put test outputs in build/
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2024-03-06 16:40:54 -08:00 |
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Fischer Moseley
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71ec1174d1
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add parameterized HW tests for all memory core modes
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2024-03-06 14:53:27 -08:00 |
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Fischer Moseley
|
d1a772784a
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add environment.sh for tool paths and serial ports
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2024-03-06 11:26:31 -08:00 |
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Fischer Moseley
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5d5a50042f
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make model tracking automatic in memory core tests
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2024-03-06 01:12:36 -08:00 |
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Fischer Moseley
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c1935bcb11
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add random memory core tests
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2024-03-05 23:59:42 -08:00 |
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Fischer Moseley
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fd22c9a9f4
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finish memory core test class
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2024-03-05 22:44:36 -08:00 |
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Fischer Moseley
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b00e4d0e60
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revert wiring.Component instead of Elaboratable
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2024-03-04 01:18:31 -08:00 |
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Fischer Moseley
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5531277c99
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even more MemoryCore tests
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2024-03-04 00:43:54 -08:00 |
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Fischer Moseley
|
f83dc59b4e
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add more MemoryCore tests
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2024-03-04 00:17:36 -08:00 |
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Fischer Moseley
|
08adbd8ede
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switch to wiring.Component instead of Elaboratable
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2024-03-03 19:10:06 -08:00 |
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Fischer Moseley
|
be79ba28b5
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define ABC for cores to inherit from
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2024-03-03 18:53:08 -08:00 |