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tests: fix logic_analyzer_sim

This commit is contained in:
Fischer Moseley 2024-08-01 07:26:55 -07:00
parent 55884a11df
commit 165c6e46ca
1 changed files with 3 additions and 2 deletions
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5
test/test_logic_analyzer_sim.py
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@ -10,6 +10,7 @@ moe = Signal(9)
la = LogicAnalyzerCore(1024, [larry, curly, moe])
la.base_addr = 0
_ = la.max_addr
async def print_data_at_addr(ctx, addr):
@ -33,7 +34,7 @@ async def print_data_at_addr(ctx, addr):
async def set_fsm_register(ctx, name, data):
addr = la._fsm.registers._memory_map[name]["addrs"][0]
strobe_addr = la._fsm.registers._base_addr
strobe_addr = la._fsm.registers.base_addr
await write_register(la, ctx, strobe_addr, 0)
await write_register(la, ctx, addr, data)
@ -43,7 +44,7 @@ async def set_fsm_register(ctx, name, data):
async def set_trig_blk_register(ctx, name, data):
addr = la._trig_blk.registers._memory_map[name]["addrs"][0]
strobe_addr = la._trig_blk.registers._base_addr
strobe_addr = la._trig_blk.registers.base_addr
await write_register(la, ctx, strobe_addr, 0)
await write_register(la, ctx, addr, data)