meta: sort imports with ruff

Makefile

@@ -3,6 +3,7 @@ test:
 	python3 -m pytest --cov
 
 format:
+	python3 -m ruff check --select I --fix
 	python3 -m ruff format
 
 clean:

examples/amaranth/uart_io_core.py

@@ -1,7 +1,8 @@
+from time import sleep
+
 from amaranth import *
 from amaranth.lib import io
 from manta import *
-from time import sleep
 
 
 class UARTIOCoreExample(Elaboratable):

examples/amaranth/uart_logic_analyzer.py

@@ -1,7 +1,8 @@
+from time import sleep
+
 from amaranth import *
 from amaranth.lib import io
 from manta import *
-from time import sleep
 
 
 class UARTLogicAnalyzerExample(Elaboratable):

examples/verilog/icestick/uart_io_core/blinky.py

@@ -1,6 +1,7 @@
-from manta import *
 from time import sleep
 
+from manta import *
+
 manta = Manta.from_config("manta.yaml")
 
 i = 0

examples/verilog/nexys4_ddr/uart_io_core/blinky.py

@@ -1,6 +1,7 @@
-from manta import *
-from time import sleep
 from random import randint
+from time import sleep
+
+from manta import *
 
 manta = Manta.from_config("manta.yaml")
 

src/manta/__init__.py

@@ -1,10 +1,10 @@
-from manta.manta import Manta
-from manta.uart import UARTInterface
-from manta.ethernet import EthernetInterface
-from manta.logic_analyzer import LogicAnalyzerCore, TriggerModes
-from manta.io_core import IOCore
-from manta.memory_core import MemoryCore
 from manta.cli import main
+from manta.ethernet import EthernetInterface
+from manta.io_core import IOCore
+from manta.logic_analyzer import LogicAnalyzerCore, TriggerModes
+from manta.manta import Manta
+from manta.memory_core import MemoryCore
+from manta.uart import UARTInterface
 
 __all__ = [
     "Manta",

src/manta/cli.py

@@ -1,8 +1,8 @@
+from importlib.metadata import distribution
+from sys import argv
+
 from manta.manta import Manta
 from manta.utils import *
-from sys import argv
-from importlib.metadata import distribution
-
 
 logo = f"""
                                         .

src/manta/ethernet/__init__.py

@@ -1,9 +1,11 @@
-from amaranth import *
-from manta.utils import *
-from manta.ethernet.source_bridge import UDPSourceBridge
-from manta.ethernet.sink_bridge import UDPSinkBridge
-from random import getrandbits
 import socket
+from random import getrandbits
+
+from amaranth import *
+
+from manta.ethernet.sink_bridge import UDPSinkBridge
+from manta.ethernet.source_bridge import UDPSourceBridge
+from manta.utils import *
 
 
 class EthernetInterface(Elaboratable):

src/manta/ethernet/liteeth_gen.py

@@ -37,31 +37,24 @@
 # Copyright (c) 2023 LumiGuide Fietsdetectie B.V. <goemansrowan@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from migen import *
-
-from litex.gen import *
-
-from litex.build.generic_platform import *
-from litex.build.xilinx.platform import XilinxPlatform
-from litex.build.lattice.platform import LatticePlatform
-
-from litex.soc.interconnect import wishbone
-from litex.soc.interconnect import axi
-from litex.soc.integration.soc_core import *
-from litex.soc.integration.builder import *
-from litex.soc.integration.soc import SoCRegion
-
-from liteeth.common import *
+from tempfile import TemporaryDirectory
 
 from liteeth import phy as liteeth_phys
-from liteeth.mac import LiteEthMAC
+from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.core.dhcp import LiteEthDHCP
-
-from liteeth.frontend.stream import LiteEthUDPStreamer
 from liteeth.frontend.etherbone import LiteEthEtherbone
-
-from tempfile import TemporaryDirectory
+from liteeth.frontend.stream import LiteEthUDPStreamer
+from liteeth.mac import LiteEthMAC
+from litex.build.generic_platform import *
+from litex.build.lattice.platform import LatticePlatform
+from litex.build.xilinx.platform import XilinxPlatform
+from litex.gen import *
+from litex.soc.integration.builder import *
+from litex.soc.integration.soc import SoCRegion
+from litex.soc.integration.soc_core import *
+from litex.soc.interconnect import axi, wishbone
+from migen import *
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -320,7 +313,7 @@ class PHYCore(SoCMini):
             if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]:
                 refclk_freq = core_config.get("refclk_freq", 0)
                 assert refclk_freq in [125e6, 156.25e6]
-                from liteeth.phy.a7_gtp import QPLLSettings, QPLL
+                from liteeth.phy.a7_gtp import QPLL, QPLLSettings
 
                 qpll_settings = QPLLSettings(
                     refclksel=0b001,

src/manta/ethernet/sink_bridge.py

@@ -1,4 +1,5 @@
 from amaranth import *
+
 from manta.utils import *
 
 

src/manta/ethernet/source_bridge.py

@@ -1,4 +1,5 @@
 from amaranth import *
+
 from manta.utils import *
 
 

src/manta/io_core.py

@@ -1,7 +1,9 @@
-from amaranth import *
-from manta.utils import *
 from math import ceil
 
+from amaranth import *
+
+from manta.utils import *
+
 
 class IOCore(MantaCore):
     """

src/manta/logic_analyzer/__init__.py

@@ -1,9 +1,10 @@
 from amaranth import *
-from manta.utils import *
-from manta.memory_core import MemoryCore
-from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
-from manta.logic_analyzer.fsm import LogicAnalyzerFSM, TriggerModes
+
 from manta.logic_analyzer.capture import LogicAnalyzerCapture
+from manta.logic_analyzer.fsm import LogicAnalyzerFSM, TriggerModes
+from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
+from manta.memory_core import MemoryCore
+from manta.utils import *
 
 import math
 

src/manta/logic_analyzer/capture.py

@@ -1,5 +1,5 @@
-from manta.logic_analyzer.playback import LogicAnalyzerPlayback
 from manta.logic_analyzer import TriggerModes
+from manta.logic_analyzer.playback import LogicAnalyzerPlayback
 
 
 class LogicAnalyzerCapture:
@@ -78,9 +78,10 @@ class LogicAnalyzerCapture:
         the core.
         """
 
-        from vcd import VCDWriter
         from datetime import datetime
 
+        from vcd import VCDWriter
+
         # Compute the timescale from the frequency of the provided clock
         half_period = 1 / (2 * self._interface._clock_freq)
         exponent = math.floor(math.log10(half_period))

src/manta/logic_analyzer/fsm.py

@@ -1,5 +1,6 @@
 from amaranth import *
 from amaranth.lib.enum import IntEnum
+
 from manta.io_core import IOCore
 
 

src/manta/logic_analyzer/trigger_block.py

@@ -1,5 +1,6 @@
 from amaranth import *
 from amaranth.lib.enum import IntEnum
+
 from manta.io_core import IOCore
 
 

src/manta/manta.py

@@ -1,11 +1,12 @@
+import yaml
 from amaranth import *
-from manta.uart import UARTInterface
+
 from manta.ethernet import EthernetInterface
 from manta.io_core import IOCore
-from manta.memory_core import MemoryCore
 from manta.logic_analyzer import LogicAnalyzerCore
+from manta.memory_core import MemoryCore
+from manta.uart import UARTInterface
 from manta.utils import *
-import yaml
 
 
 class Manta(Elaboratable):

src/manta/memory_core.py

@@ -1,8 +1,10 @@
-from amaranth import *
-from manta.utils import *
-from amaranth.lib.memory import Memory
 from math import ceil
 
+from amaranth import *
+from amaranth.lib.memory import Memory
+
+from manta.utils import *
+
 
 class MemoryCore(MantaCore):
     """

src/manta/uart/__init__.py

@@ -1,11 +1,12 @@
 from amaranth import *
-from manta.utils import *
-from manta.uart.receiver import UARTReceiver
-from manta.uart.receive_bridge import ReceiveBridge
-from manta.uart.transmitter import UARTTransmitter
-from manta.uart.transmit_bridge import TransmitBridge
 from serial import Serial
 
+from manta.uart.receive_bridge import ReceiveBridge
+from manta.uart.receiver import UARTReceiver
+from manta.uart.transmit_bridge import TransmitBridge
+from manta.uart.transmitter import UARTTransmitter
+from manta.utils import *
+
 
 class UARTInterface(Elaboratable):
     """
@@ -127,7 +128,7 @@ class UARTInterface(Elaboratable):
 
         if ports[0].serial_number != ports[1].serial_number:
             raise ValueError(
-                f"Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices."
+                "Serial numbers should be the same on both FT2232 ports - probably somehow grabbed ports on two different devices."
             )
 
         if ports[0].location > ports[1].location:

src/manta/uart/receive_bridge.py

@@ -1,6 +1,6 @@
 from amaranth import *
-from amaranth.lib.enum import IntEnum
 from amaranth.lib.data import ArrayLayout
+from amaranth.lib.enum import IntEnum
 
 
 class States(IntEnum):

src/manta/utils.py

@@ -1,10 +1,11 @@
+import os
+from abc import ABC, abstractmethod
+from pathlib import Path
+from random import sample
+
 from amaranth import Elaboratable
 from amaranth.lib import data
 from amaranth.sim import Simulator
-from abc import ABC, abstractmethod
-from random import sample
-from pathlib import Path
-import os
 
 
 class MantaCore(ABC, Elaboratable):

test/test_bridge_rx_sim.py

@@ -1,7 +1,6 @@
 from manta.uart import ReceiveBridge
 from manta.utils import *
 
-
 bridge_rx = ReceiveBridge()
 
 

test/test_bridge_tx_sim.py

@@ -1,7 +1,7 @@
-from manta.uart import TransmitBridge
-from manta.utils import *
 from random import sample
 
+from manta.uart import TransmitBridge
+from manta.utils import *
 
 bridge_tx = TransmitBridge()
 

test/test_config_export.py

@@ -1,8 +1,8 @@
+import tempfile
+
+import yaml
 from amaranth import *
 from manta import *
-import tempfile
-import os
-import yaml
 
 
 def test_io_core_dump():

test/test_examples_build.py

@@ -1,7 +1,8 @@
-import subprocess
-import pytest
-import sys
 import os
+import subprocess
+import sys
+
+import pytest
 
 verilog_root_dirs = [
     "examples/verilog/icestick/uart_io_core",
@@ -28,14 +29,14 @@ parent_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
 sys.path.insert(0, parent_dir)
 
 # Import Examples
-from examples.amaranth.uart_io_core import UARTIOCoreExample
-from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
-from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
-
 # Import Platforms
 from amaranth_boards.icestick import ICEStickPlatform
 from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 
+from examples.amaranth.uart_io_core import UARTIOCoreExample
+from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
+from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
+
 # Manually specify a list of examples/platforms to test.
 
 # This is necessary as some examples don't work without some amount of onboard

test/test_io_core_hw.py

@@ -1,12 +1,13 @@
+import os
+from random import getrandbits
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from manta import *
 from manta.utils import *
-import pytest
-from random import getrandbits
-import os
 
 
 class IOCoreLoopbackTest(Elaboratable):

test/test_io_core_sim.py

@@ -1,7 +1,8 @@
+from random import getrandbits
+
 from amaranth import *
 from manta import *
 from manta.utils import *
-from random import getrandbits
 
 probe0 = Signal(1)
 probe1 = Signal(2)

test/test_logic_analyzer_hw.py

@@ -1,11 +1,12 @@
+import os
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from manta import *
 from manta.utils import *
-import pytest
-import os
 
 
 class LogicAnalyzerCounterTest(Elaboratable):

test/test_logic_analyzer_sim.py

@@ -2,7 +2,6 @@ from amaranth import *
 from manta.logic_analyzer import LogicAnalyzerCore
 from manta.logic_analyzer.trigger_block import Operations
 from manta.utils import *
-from random import sample
 
 larry = Signal(1)
 curly = Signal(3)

test/test_mem_core_hw.py

@@ -1,13 +1,13 @@
+import os
+from random import getrandbits
+
+import pytest
 from amaranth import *
 from amaranth.lib import io
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 from manta import *
 from manta.utils import *
-import pytest
-from random import getrandbits
-from math import ceil, log2
-import os
 
 
 class MemoryCoreLoopbackTest(Elaboratable):

test/test_mem_core_sim.py

@@ -1,8 +1,9 @@
+from math import ceil
+from random import choice, getrandbits, randint
+
+import pytest
 from manta.memory_core import MemoryCore
 from manta.utils import *
-from random import randint, choice, getrandbits
-from math import ceil
-import pytest
 
 
 class MemoryCoreTests:

test/test_source_bridge_sim.py

@@ -1,7 +1,6 @@
 from manta.ethernet import UDPSourceBridge
 from manta.utils import *
 
-
 source_bridge = UDPSourceBridge()
 
 

test/test_toolchains.py

@@ -1,8 +1,8 @@
-from amaranth_boards.test.blinky import *
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
-from amaranth_boards.icestick import ICEStickPlatform
-from manta.utils import *
 import pytest
+from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
+from amaranth_boards.test.blinky import *
+from manta.utils import *
 
 
 @pytest.mark.skipif(not xilinx_tools_installed(), reason="no toolchain installed")

test/test_uart_rx_sim.py

@@ -1,7 +1,6 @@
 from manta.uart import UARTReceiver
 from manta.utils import *
 
-
 uart_rx = UARTReceiver(clocks_per_baud=10)
 
 

test/test_uart_tx_sim.py

@@ -1,7 +1,6 @@
 from manta.uart import UARTTransmitter
 from manta.utils import *
 
-
 uart_tx = UARTTransmitter(clocks_per_baud=10)
 
 

test/test_verilog_gen.py

@@ -1,6 +1,7 @@
-from manta.cli import gen, inst
-import tempfile
 import os
+import tempfile
+
+from manta.cli import gen, inst
 
 
 def test_verilog_gen():