meta: switch from black to ruff

.github/workflows/run_tests.yml

@@ -28,7 +28,7 @@ jobs:
       - name: Check formatting
         run: |
           source venv/bin/activate
-          python3 -m black . --check
+          python3 -m ruff format --check
 
       - name: Run tests
         run: |

Makefile

@@ -3,7 +3,7 @@ test:
 	python3 -m pytest --cov
 
 format:
-	python3 -m black .
+	python3 -m ruff format
 
 clean:
 	git clean -Xdf

README.md

@@ -4,7 +4,7 @@
 ![run_tests](https://github.com/fischermoseley/manta/actions/workflows/run_tests.yml/badge.svg)
 ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg)
 [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0)
-[![Code style: black](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black)
+[![Ruff](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/astral-sh/ruff/main/assets/badge/v2.json)](https://github.com/astral-sh/ruff)
 
 Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.
 

src/manta/logic_analyzer/playback.py

@@ -52,7 +52,6 @@ class LogicAnalyzerPlayback(Elaboratable):
         # Assign the probe values by part-selecting from the data port
         lower = 0
         for p in reversed(self._probes):
-
             # Set output probe to zero if we're not
             with m.If(self.valid):
                 m.d.comb += p.eq(read_port.data[lower : lower + len(p)])

src/manta/manta.py

@@ -28,7 +28,6 @@ class Manta(Elaboratable):
 
     @classmethod
     def from_config(cls, config_path):
-
         # Load config from YAML
         extension = config_path.split(".")[-1]
         if extension not in ["yaml", "yml"]:

test/test_mem_core_hw.py

@@ -78,7 +78,6 @@ class MemoryCoreLoopbackTest(Elaboratable):
 
         if self.mode in ["bidirectional", "host_to_fpga"]:
             for addr in jumble(range(self.depth)):
-
                 # Write a random balue to a random bus address
                 data = getrandbits(self.width)
                 self.manta.cores.mem.write(addr, data)
@@ -92,7 +91,6 @@ class MemoryCoreLoopbackTest(Elaboratable):
 
         if self.mode in ["bidirectional", "fpga_to_host"]:
             for addr in jumble(range(self.depth)):
-
                 # Write a random value to a random user address
                 data = getrandbits(self.width)
                 self.write_user_side(addr, data)

test/test_mem_core_sim.py

@@ -77,7 +77,6 @@ class MemoryCoreTests:
         # random reads and writes in random orders
         for _ in range(5):
             for addr in jumble(self.bus_addrs):
-
                 operation = choice(["read", "write"])
                 if operation == "read":
                     await self.verify_bus_side(addr)
@@ -101,7 +100,6 @@ class MemoryCoreTests:
     async def multi_user_write_then_multi_bus_reads(self):
         # write-write-write then read-read-read
         for user_addr in jumble(self.user_addrs):
-
             # write a random number to the user side
             data = getrandbits(self.width)
             await self.write_user_side(user_addr, data)
@@ -193,7 +191,6 @@ class MemoryCoreTests:
         # random reads and writes in random orders
         for _ in range(5):
             for user_addr in jumble(self.user_addrs):
-
                 operation = choice(["read", "write"])
                 if operation == "read":
                     await self.verify_user_side(user_addr)