cli: remove JSON loader, add test for instantiation generation

src/manta/cli.py

@@ -78,13 +78,13 @@ def inst(config_path):
     ports = manta.get_top_level_ports()
     hdl = ",\n    ".join([f".{p.name}({p.name})" for p in ports])
 
-    foo = """
+    header = """
 manta manta_inst(
     .clk(clk),
     .rst(rst),
     """
 
-    print(foo + hdl + ");\n")
+    return header + hdl + ");\n"
 
 
 def capture(config_path, logic_analyzer_name, export_paths):
@@ -139,7 +139,7 @@ def main():
         if len(argv) != 3:
             wrong_args()
 
-        inst(argv[2])
+        print(inst(argv[2]))
 
     elif argv[1] == "capture":
         if len(argv) < 5:

src/manta/manta.py

@@ -6,7 +6,6 @@ from manta.memory_core import MemoryCore
 from manta.logic_analyzer import LogicAnalyzerCore
 from manta.utils import *
 import yaml
-import json
 
 
 class Manta(Elaboratable):
@@ -30,19 +29,15 @@ class Manta(Elaboratable):
     @classmethod
     def from_config(cls, config_path):
 
-        # Load config from either YAML or JSON
+        # Load config from YAML
         extension = config_path.split(".")[-1]
-        if extension not in ["yaml", "yml", "json"]:
+        if extension not in ["yaml", "yml"]:
             raise ValueError(
                 f"Configuration file {config_path} has unrecognized file type."
             )
 
         with open(config_path, "r") as f:
-            if extension in ["yaml", "yml"]:
-                config = yaml.safe_load(f)
-
-            elif extension in ["json"]:
-                config = json.load(f)
+            config = yaml.safe_load(f)
 
         # Validate config
         if "cores" not in config:

test/test_verilog_gen.py

@@ -1,4 +1,4 @@
-from manta.cli import gen
+from manta.cli import gen, inst
 import tempfile
 import os
 
@@ -11,3 +11,10 @@ def test_verilog_gen():
 
         if not os.path.isfile(tmp_dir + "/manta.v"):
             raise ValueError("No Verilog file generated!")
+
+
+def test_inst_gen():
+    inst_string = inst("test/test_verilog_gen.yaml")
+
+    if not inst_string:
+        raise ValueError("No Verilog instantiation generated!")