A configurable and approachable tool for FPGA debugging and rapid prototyping.
Go to file
Fischer Moseley 62049bac84 meta: replace Signal(1) with Signal() 2026-01-19 16:31:12 -07:00
.github meta: rename environment.sh to .env, add nextpnr-gowin 2025-11-04 15:25:09 -07:00
doc uart: fix #36, explicitly handle scientific notation in YAML config 2025-04-06 18:28:29 -06:00
examples meta: replace Signal(1) with Signal() 2026-01-19 16:31:12 -07:00
src/manta meta: replace Signal(1) with Signal() 2026-01-19 16:31:12 -07:00
test meta: replace Signal(1) with Signal() 2026-01-19 16:31:12 -07:00
.env meta: rename environment.sh to .env, add nextpnr-gowin 2025-11-04 15:25:09 -07:00
.gitignore gitignore: tidy and remove unnecessary per-directory gitignores 2026-01-14 14:10:27 -07:00
.pre-commit-config.yaml meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
LICENSE.txt meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
Makefile ci: remove unnecessary codecov.yml 2024-11-29 11:05:47 -07:00
README.md docs: use absolute logo path 2024-12-03 20:05:26 -08:00
mkdocs.yml docs: update memory_core 2024-10-08 11:42:10 -06:00
pyproject.toml meta: update pyproject.toml 2024-12-03 19:50:04 -08:00

README.md

Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping

run_tests build_docs codecov License: GPL v3 Ruff

Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.

For more information check out the docs: https://fischermoseley.github.io/manta