uart: use wiring.Component for internal bus
This commit is contained in:
Fischer Moseley
parent
31d11aff19
commit
28be273828
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@ -6,15 +6,11 @@ from manta.utils import *
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class EthernetBridge(wiring.Component):
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sink: In(StreamSignature(32))
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source: Out(StreamSignature(32))
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sink: In(StreamSignature(32))
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def __init__(self):
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super().__init__()
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# TODO: use In() and Out() for InternalBus connections
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self.bus_o = Signal(InternalBus())
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self.bus_i = Signal(InternalBus())
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bus_source: Out(InternalBusSignature)
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bus_sink: In(InternalBusSignature)
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def elaborate(self, platform):
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m = Module()
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@ -79,14 +75,14 @@ class EthernetBridge(wiring.Component):
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with m.If(self.sink.valid):
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# we have the length and the address to read from, let's go!
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m.d.sync += self.bus_o.addr.eq(self.sink.data)
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m.d.sync += self.bus_o.data.eq(0)
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m.d.sync += self.bus_o.rw.eq(0)
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m.d.sync += self.bus_o.valid.eq(1)
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m.d.sync += self.bus_source.p.addr.eq(self.sink.data)
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m.d.sync += self.bus_source.p.data.eq(0)
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m.d.sync += self.bus_source.p.rw.eq(0)
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m.d.sync += self.bus_source.p.valid.eq(1)
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with m.If(read_len == 0):
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# we've sent the last read request in this batch to the bus
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m.d.sync += self.bus_o.last.eq(1)
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m.d.sync += self.bus_source.p.last.eq(1)
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m.d.sync += read_len.eq(0)
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m.next = "READ"
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@ -96,22 +92,22 @@ class EthernetBridge(wiring.Component):
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# Clock out read requests to the bus
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with m.If(read_len > 0):
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m.d.sync += self.bus_o.addr.eq(self.bus_o.addr + 1)
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m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
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m.d.sync += read_len.eq(read_len - 1)
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with m.If(read_len == 1):
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m.d.sync += self.bus_o.last.eq(1)
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m.d.sync += self.bus_source.p.last.eq(1)
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with m.Else():
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m.d.sync += self.bus_o.eq(
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m.d.sync += self.bus_source.p.eq(
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0
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) # TODO: it's probably overzealous to set the whole bus to zero, but it makes debugging easy so we're doing it xD
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# Clock out any read data from the bus
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with m.If(self.bus_i.valid):
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m.d.sync += self.source.data.eq(self.bus_i.data)
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with m.If(self.bus_sink.p.valid):
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m.d.sync += self.source.data.eq(self.bus_sink.p.data)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(self.bus_i.last)
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m.d.sync += self.source.last.eq(self.bus_sink.p.last)
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with m.If(self.source.last):
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m.d.sync += self.source.data.eq(0)
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@ -121,17 +117,17 @@ class EthernetBridge(wiring.Component):
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with m.State("WRITE_WAIT_FOR_ADDR"):
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with m.If(self.sink.valid):
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m.d.sync += self.bus_o.addr.eq(self.sink.data)
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m.d.sync += self.bus_source.p.addr.eq(self.sink.data)
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m.next = "WRITE_FIRST"
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# Don't want to increment address on the first write,
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# and I'm lazy so I'm making a new state to keep track of that
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with m.State("WRITE_FIRST"):
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with m.If(self.sink.valid):
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m.d.sync += self.bus_o.data.eq(self.sink.data)
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m.d.sync += self.bus_o.rw.eq(1)
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m.d.sync += self.bus_o.valid.eq(1)
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m.d.sync += self.bus_o.last.eq(self.sink.last)
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m.d.sync += self.bus_source.p.data.eq(self.sink.data)
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m.d.sync += self.bus_source.p.rw.eq(1)
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m.d.sync += self.bus_source.p.valid.eq(1)
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m.d.sync += self.bus_source.p.last.eq(self.sink.last)
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with m.If(self.sink.last):
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m.d.sync += self.sink.ready.eq(0)
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@ -142,11 +138,11 @@ class EthernetBridge(wiring.Component):
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with m.State("WRITE"):
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with m.If(self.sink.valid):
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m.d.sync += self.bus_o.addr.eq(self.bus_o.addr + 1)
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m.d.sync += self.bus_o.data.eq(self.sink.data)
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m.d.sync += self.bus_o.rw.eq(1)
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m.d.sync += self.bus_o.valid.eq(1)
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m.d.sync += self.bus_o.last.eq(self.sink.last)
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m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
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m.d.sync += self.bus_source.p.data.eq(self.sink.data)
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m.d.sync += self.bus_source.p.rw.eq(1)
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m.d.sync += self.bus_source.p.valid.eq(1)
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m.d.sync += self.bus_source.p.last.eq(self.sink.last)
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with m.If(self.sink.last):
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m.d.sync += self.sink.ready.eq(0)
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@ -159,9 +155,9 @@ class EthernetBridge(wiring.Component):
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m.next = "WRITE"
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with m.State("WRITE_WAIT_FOR_LAST"):
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m.d.sync += self.bus_o.eq(0)
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m.d.sync += self.bus_source.p.eq(0)
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with m.If(self.bus_i.last):
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with m.If(self.bus_sink.p.last):
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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m.d.sync += self.source.data.eq(
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EthernetMessageHeader.concat_signals(
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@ -13,6 +13,9 @@ class MemoryCore(MantaCore):
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and the other provided to user logic.
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"""
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bus_source: Out(InternalBusSignature)
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bus_sink: In(InternalBusSignature)
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def __init__(self, mode, width, depth):
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"""
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Create a Memory Core with the given width and depth.
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@ -33,46 +36,28 @@ class MemoryCore(MantaCore):
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depth (int): The depth of the memory, in entries.
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"""
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super().__init__()
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self._mode = mode
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self._width = width
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self._depth = depth
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self._n_mems = ceil(self._width / 32)
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# Bus Connections
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self.bus_i = Signal(InternalBus())
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self.bus_o = Signal(InternalBus())
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# User Ports
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if self._mode == "fpga_to_host":
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self.user_addr = Signal(range(self._depth))
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self.user_data_in = Signal(self._width)
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self.user_write_enable = Signal()
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self._top_level_ports = [
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self.user_addr,
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self.user_data_in,
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self.user_write_enable,
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]
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elif self._mode == "host_to_fpga":
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self.user_addr = Signal(range(self._depth))
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self.user_data_out = Signal(self._width)
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self._top_level_ports = [
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self.user_addr,
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self.user_data_out,
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]
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elif self._mode == "bidirectional":
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self.user_addr = Signal(range(self._depth))
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self.user_data_in = Signal(self._width)
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self.user_data_out = Signal(self._width)
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self.user_write_enable = Signal()
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self._top_level_ports = [
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self.user_addr,
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self.user_data_in,
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self.user_data_out,
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self.user_write_enable,
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]
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# Define memories
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n_full = self._width // 32
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@ -87,10 +72,6 @@ class MemoryCore(MantaCore):
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Memory(shape=n_partial, depth=self._depth, init=[0] * self._depth)
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]
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@property
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def top_level_ports(self):
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return self._top_level_ports
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@property
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def max_addr(self):
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return self.base_addr + (self._depth * self._n_mems)
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@ -155,11 +136,11 @@ class MemoryCore(MantaCore):
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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(self.bus_sink.p.valid)
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& (self.bus_sink.p.addr >= start_addr)
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& (self.bus_sink.p.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += read_port.addr.eq(self.bus_sink.p.addr - start_addr)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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@ -168,7 +149,7 @@ class MemoryCore(MantaCore):
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_o.data.eq(read_port.data)
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m.d.sync += self.bus_source.p.data.eq(read_port.data)
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elif self._mode == "host_to_fpga":
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write_port = mem.write_port()
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@ -176,13 +157,13 @@ class MemoryCore(MantaCore):
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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(self.bus_sink.p.valid)
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& (self.bus_sink.p.addr >= start_addr)
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& (self.bus_sink.p.addr <= stop_addr)
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):
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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m.d.sync += write_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_sink.p.data)
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m.d.sync += write_port.en.eq(self.bus_sink.p.rw)
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elif self._mode == "bidirectional":
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read_port = mem.read_port()
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@ -193,14 +174,14 @@ class MemoryCore(MantaCore):
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# Throw BRAM operations into the front of the pipeline
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with m.If(
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(self.bus_i.valid)
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& (self.bus_i.addr >= start_addr)
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& (self.bus_i.addr <= stop_addr)
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(self.bus_sink.p.valid)
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& (self.bus_sink.p.addr >= start_addr)
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& (self.bus_sink.p.addr <= stop_addr)
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):
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m.d.sync += read_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.addr.eq(self.bus_i.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_i.data)
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m.d.sync += write_port.en.eq(self.bus_i.rw)
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m.d.sync += read_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += write_port.addr.eq(self.bus_sink.p.addr - start_addr)
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m.d.sync += write_port.data.eq(self.bus_sink.p.data)
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m.d.sync += write_port.en.eq(self.bus_sink.p.rw)
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# Pull BRAM reads from the back of the pipeline
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with m.If(
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@ -209,7 +190,7 @@ class MemoryCore(MantaCore):
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& (self._bus_pipe[2].addr >= start_addr)
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& (self._bus_pipe[2].addr <= stop_addr)
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):
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m.d.sync += self.bus_o.data.eq(read_port.data)
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m.d.sync += self.bus_source.p.data.eq(read_port.data)
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def _tie_mems_to_user_logic(self, m):
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# Handle write ports
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@ -239,13 +220,15 @@ class MemoryCore(MantaCore):
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m.submodules[f"mem_{i}"] = mem
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# Pipeline the bus to accommodate the two clock-cycle delay in the memories
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self._bus_pipe = [Signal(InternalBus()) for _ in range(3)]
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m.d.sync += self._bus_pipe[0].eq(self.bus_i)
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self._bus_pipe = [
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Signal(InternalBusLayout, name=f"bus_pipe_{i}") for i in range(3)
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]
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m.d.sync += self._bus_pipe[0].eq(self.bus_sink.p)
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for i in range(1, 3):
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m.d.sync += self._bus_pipe[i].eq(self._bus_pipe[i - 1])
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m.d.sync += self.bus_o.eq(self._bus_pipe[2])
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m.d.sync += self.bus_source.p.eq(self._bus_pipe[1])
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self._tie_mems_to_bus(m)
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self._tie_mems_to_user_logic(m)
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@ -11,12 +11,19 @@ from manta.uart.transmitter import UARTTransmitter
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from manta.utils import *
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class UARTInterface(Elaboratable):
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class UARTInterface(wiring.Component):
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"""
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A synthesizable module for UART communication between a host machine and
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the FPGA.
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"""
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# Top-Level Ports
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rx: In(1)
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tx: Out(1)
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bus_source: Out(InternalBusSignature)
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bus_sink: In(InternalBusSignature)
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def __init__(self, port, baudrate, clock_freq, stall_interval=16, chunk_size=256):
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"""
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This function is the main mechanism for configuring a UART Interface
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@ -60,6 +67,7 @@ class UARTInterface(Elaboratable):
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provided, or the clock frequency or baudrate is invalid.
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"""
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super().__init__()
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self._port = port
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self._baudrate = baudrate
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@ -69,13 +77,6 @@ class UARTInterface(Elaboratable):
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self._stall_interval = stall_interval
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self._check_config()
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# Top-Level Ports
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self.rx = Signal()
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self.tx = Signal()
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self.bus_o = Signal(InternalBus())
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self.bus_i = Signal(InternalBus())
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@classmethod
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def from_config(cls, config):
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integer_options = [
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@ -196,13 +197,6 @@ class UARTInterface(Elaboratable):
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self._serial_device = Serial(chosen_port, self._baudrate, timeout=1)
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return self._serial_device
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def get_top_level_ports(self):
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"""
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Return the Amaranth signals that should be included as ports in the
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top-level Manta module.
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"""
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return [self.rx, self.tx]
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@property
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def clock_freq(self):
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return self._clock_freq
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@ -343,8 +337,7 @@ class UARTInterface(Elaboratable):
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wiring.connect(m, cobs_encode.source, uart_tx.sink)
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m.d.comb += self.tx.eq(uart_tx.tx)
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# TODO: replace these with wiring.Connect
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m.d.comb += self.bus_o.eq(bridge.bus_o)
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m.d.comb += bridge.bus_i.eq(self.bus_i)
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wiring.connect(m, bridge.bus_source, wiring.flipped(self.bus_source))
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wiring.connect(m, wiring.flipped(self.bus_sink), bridge.bus_sink)
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return m
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@ -11,7 +11,7 @@ from amaranth.lib.wiring import In, Out
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from amaranth.sim import Simulator
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class MantaCore(ABC, Elaboratable):
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class MantaCore(ABC, wiring.Component):
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# These attributes are meant to be settable and gettable, but max_addr and
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# top_level_ports are intended to be only gettable. Do not implement
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# setters for them in subclasses.
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@ -29,15 +29,6 @@ class MantaCore(ABC, Elaboratable):
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"""
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pass
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@property
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@abstractmethod
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def top_level_ports(self):
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"""
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Return the Amaranth signals that should be included as ports in the
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top-level Manta module.
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"""
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pass
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@abstractmethod
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def to_config(self):
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"""
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@ -87,22 +78,17 @@ class CoreContainer:
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self._last_used_addr = value.max_addr + 1
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class InternalBus(data.StructLayout):
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"""
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Describes the layout of Manta's internal bus, such that signals of
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the appropriate dimension can be instantiated with Signal(InternalBus()).
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"""
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InternalBusLayout = data.StructLayout(
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{
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"addr": 32,
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"data": 32,
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"rw": 1,
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"valid": 1,
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"last": 1,
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}
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)
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def __init__(self):
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super().__init__(
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{
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"addr": 32,
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"data": 32,
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"rw": 1,
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"valid": 1,
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"last": 1,
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}
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)
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InternalBusSignature = wiring.Signature({"p": Out(InternalBusLayout)})
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class StreamSignature(wiring.Signature):
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@ -26,8 +26,8 @@ class UARTHardwarePlusMemoryCore(wiring.Component):
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# the _clocks_per_baud attribute
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self.uart = uart
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m.d.comb += uart.bus_i.eq(mem_core.bus_o)
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m.d.comb += mem_core.bus_i.eq(uart.bus_o)
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wiring.connect(m, uart.bus_source, mem_core.bus_sink)
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wiring.connect(m, mem_core.bus_source, uart.bus_sink)
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m.d.comb += self.tx.eq(uart.tx)
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m.d.comb += uart.rx.eq(self.rx)
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Reference in New Issue