uart: remove flaky nexys4ddr baudrate mismatch test case

2024-09-22 18:45:06 -07:00 · 2024-09-22 18:45:06 -07:00 · cfbf372862
parent d450221ed8
commit cfbf372862
1 changed files with 0 additions and 1 deletions
--- a/test/test_uart_baud_mismatch.py
+++ b/test/test_uart_baud_mismatch.py
@ -103,7 +103,6 @@ def test_baudrate_mismatch_xilinx_passes(baudrate, percent_slowdown, stall_inter


 nexys4ddr_fail_cases = [
-    (3e6, 1, 1024),  # Light clock mismatch, no mitigation
    (3e6, 2, 1024),  # Heavy clock mismatch, no mitigation
    (3e6, 2, 16),  # Heavy clock mismatch, light mitigation
 ]