uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
This commit is contained in:
Fischer Moseley
parent
de6ce45f2e
commit
614c3a5d7b
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from amaranth import *
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class COBSDecode(Elaboratable):
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def __init__(self):
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# Stream-like data input
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self.data_i = Signal(8)
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self.valid_i = Signal()
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# Stream-like data output
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self.data_o = Signal(8)
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self.valid_o = Signal()
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self.last_o = Signal()
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def elaborate(self, platform):
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m = Module()
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counter = Signal(8)
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m.d.sync += self.data_o.eq(0)
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m.d.sync += self.valid_o.eq(0)
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m.d.sync += self.last_o.eq(0)
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# State Machine:
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with m.FSM():
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with m.State("WAIT_FOR_PACKET_START"):
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with m.If((self.data_i == 0) & (self.valid_i)):
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m.next = "START_OF_PACKET"
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with m.State("START_OF_PACKET"):
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with m.If(self.valid_i):
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m.d.sync += counter.eq(self.data_i - 1)
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m.next = "DECODING"
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with m.Else():
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m.next = "START_OF_PACKET"
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with m.State("DECODING"):
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with m.If(self.valid_i):
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with m.If(counter > 0):
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m.d.sync += counter.eq(counter - 1)
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m.d.sync += self.data_o.eq(self.data_i)
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m.d.sync += self.valid_o.eq(1)
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m.next = "DECODING"
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with m.Else():
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with m.If(self.data_i == 0):
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m.d.sync += self.last_o.eq(1)
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m.next = "START_OF_PACKET"
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with m.Else():
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m.d.sync += counter.eq(self.data_i - 1)
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m.d.sync += self.valid_o.eq(1)
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m.next = "DECODING"
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return m
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from amaranth import *
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from amaranth.lib.memory import Memory
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class COBSEncode(Elaboratable):
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def __init__(self):
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# Top-Level IO
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self.start = Signal()
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self.done = Signal()
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# Stream-like data input
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self.data_i = Signal(8)
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self.valid_i = Signal()
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self.ready_o = Signal()
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# Stream-like data output
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self.data_o = Signal(8)
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self.valid_o = Signal()
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self.ready_i = Signal()
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# Define memory
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self.memory = Memory(shape=8, depth=256, init=[0] * 256)
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def elaborate(self, platform):
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m = Module()
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# Internal Signals
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head_pointer = Signal(range(256))
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tail_pointer = Signal(range(256))
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# Add memory and read/write ports
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m.submodules.memory = self.memory
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rd_port = self.memory.read_port()
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wr_port = self.memory.write_port()
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# Reset top-level IO
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m.d.sync += self.data_o.eq(0)
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m.d.sync += self.valid_o.eq(0)
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# Generate rd_port_addr_prev
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rd_port_addr_prev = Signal().like(rd_port.addr)
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m.d.sync += rd_port_addr_prev.eq(rd_port.addr)
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# State Machine:
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with m.FSM() as fsm:
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with m.State("IDLE"):
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with m.If(self.start):
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m.d.sync += head_pointer.eq(0)
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m.d.sync += tail_pointer.eq(0)
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m.d.sync += rd_port.addr.eq(0)
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m.next = "SEARCH_FOR_ZERO"
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with m.State("SEARCH_FOR_ZERO"):
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# Drive read addr until length is reached
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with m.If(rd_port.addr < wr_port.addr):
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m.d.sync += rd_port.addr.eq(rd_port.addr + 1)
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# Watch prev_addr and data
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with m.If((rd_port_addr_prev == wr_port.addr) | (rd_port.data == 0)):
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# Either reached the end of the input buffer or found a zero
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m.d.sync += head_pointer.eq(rd_port_addr_prev)
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m.d.sync += rd_port.addr.eq(tail_pointer)
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m.d.sync += self.data_o.eq(rd_port_addr_prev - tail_pointer + 1)
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m.d.sync += self.valid_o.eq(1)
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m.next = "CLOCK_OUT_BYTES_STALL"
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with m.Else():
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m.next = "SEARCH_FOR_ZERO"
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with m.State("CLOCK_OUT_BYTES_STALL"):
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m.d.sync += rd_port.addr.eq(rd_port.addr + 1)
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m.next = "CLOCK_OUT_BYTES"
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with m.State("CLOCK_OUT_BYTES"):
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# Drive rd_port.addr
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with m.If(rd_port.addr < head_pointer):
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m.d.sync += rd_port.addr.eq(rd_port.addr + 1)
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# Watch prev_addr
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with m.If(rd_port_addr_prev <= head_pointer):
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m.d.sync += self.data_o.eq(rd_port.data)
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m.d.sync += self.valid_o.eq(1)
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m.next = "CLOCK_OUT_BYTES"
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with m.If(rd_port_addr_prev == head_pointer):
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# Reached end of message
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with m.If(head_pointer == wr_port.addr):
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m.d.sync += self.data_o.eq(0)
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m.d.sync += self.valid_o.eq(1)
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m.next = "IDLE"
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with m.Else(): # this section is a beautiful!
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m.d.sync += tail_pointer.eq(head_pointer + 1)
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m.d.sync += head_pointer.eq(head_pointer + 1)
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m.d.sync += rd_port.addr.eq(head_pointer + 1)
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m.d.sync += self.valid_o.eq(0) # i have no idea why this works
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m.next = "SEARCH_FOR_ZERO_STALL"
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with m.State("SEARCH_FOR_ZERO_STALL"):
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m.next = "SEARCH_FOR_ZERO"
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# Fill memory from input stream
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m.d.comb += wr_port.en.eq((fsm.ongoing("IDLE")) & (self.valid_i))
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m.d.comb += wr_port.data.eq(self.data_i)
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m.d.sync += wr_port.addr.eq(wr_port.addr + wr_port.en)
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return m
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@ -0,0 +1,17 @@
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from amaranth import *
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class StreamPacker(Elaboratable):
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def __init__(self):
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self.data_i = Signal(8)
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self.valid_i = Signal()
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self.last_i = Signal()
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self.data_o = Signal(32)
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self.valid_o = Signal()
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self.ready_i = Signal()
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self.last_o = Signal()
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def elaborate(self, platform):
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m = Module()
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return m
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@ -0,0 +1,18 @@
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from amaranth import *
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class StreamUnpacker(Elaboratable):
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def __init__(self):
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self.data_i = Signal(32)
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self.valid_i = Signal()
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self.ready_o = Signal()
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self.last_i = Signal()
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self.data_o = Signal(8)
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self.valid_o = Signal()
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self.ready_i = Signal()
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self.last_o = Signal()
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def elaborate(self, platform):
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m = Module()
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return m
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from amaranth import *
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from manta.ethernet.bridge import EthernetBridge
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from manta.uart.cobs_decode import COBSDecode
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from manta.uart.cobs_encode import COBSEncode
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from manta.uart.receiver import UARTReceiver
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from manta.uart.stream_packer import StreamPacker
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from manta.uart.stream_unpacker import StreamUnpacker
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from manta.uart.transmitter import UARTTransmitter
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from manta.utils import *
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# uart_rx -> COBS decode -> pack_stream -> bridge -> unpack_stream -> COBS encode -> uart_tx
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class UARTHardware(Elaboratable):
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def __init__(self):
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self.rx = Signal()
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self.tx = Signal()
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self.bus_o = Signal(InternalBus())
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self.bus_i = Signal(InternalBus())
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self._clocks_per_baud = 10
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def elaborate(self, platform):
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m = Module()
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m.submodules.uart_rx = uart_rx = UARTReceiver(self._clocks_per_baud)
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m.submodules.cobs_decode = cobs_decode = COBSDecode()
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m.submodules.stream_packer = stream_packer = StreamPacker()
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m.submodules.bridge = bridge = EthernetBridge()
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m.submodules.stream_unpacker = stream_unpacker = StreamUnpacker()
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m.submodules.cobs_encode = cobs_encode = COBSEncode()
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m.submodules.uart_tx = uart_tx = UARTTransmitter(self._clocks_per_baud)
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m.d.comb += [
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uart_rx.rx.eq(self.rx),
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cobs_decode.data_i.eq(uart_rx.data_o),
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cobs_decode.valid_i.eq(uart_rx.valid_o),
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stream_packer.data_i.eq(cobs_decode.data_o),
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stream_packer.valid_i.eq(cobs_decode.valid_o),
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stream_packer.last_i.eq(cobs_decode.last_o),
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bridge.data_i.eq(stream_packer.data_o),
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stream_packer.ready_i.eq(bridge.ready_o),
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bridge.valid_i.eq(stream_packer.valid_o),
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bridge.last_i.eq(stream_packer.last_o),
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stream_unpacker.data_i.eq(bridge.data_o),
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bridge.ready_i.eq(stream_unpacker.ready_o),
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stream_unpacker.valid_i.eq(bridge.valid_o),
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stream_unpacker.last_i.eq(bridge.last_o),
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cobs_encode.data_i.eq(stream_unpacker.data_o),
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cobs_encode.valid_i.eq(stream_unpacker.valid_o),
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# not quite sure what the rest of these signals will be...
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uart_tx.data_i.eq(cobs_encode.data_o),
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uart_tx.start_i.eq(cobs_encode.valid_o),
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cobs_encode.ready_i.eq(uart_tx.done_o),
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self.tx.eq(uart_tx.tx),
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self.bus_o.eq(bridge.bus_o),
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bridge.bus_i.eq(self.bus_i),
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]
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return m
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uart_hw = UARTHardware()
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async def send_byte(ctx, module, data):
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# 8N1 serial, LSB sent first
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data_bits = "0" + f"{data:08b}"[::-1] + "1"
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data_bits = [int(bit) for bit in data_bits]
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for i in range(10 * uart_hw._clocks_per_baud):
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bit_index = i // uart_hw._clocks_per_baud
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ctx.set(module.rx, data_bits[bit_index])
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await ctx.tick()
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@simulate(uart_hw)
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async def test_read_request(ctx):
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await send_byte(ctx, uart_hw, 0)
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await ctx.tick()
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