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313 Commits

Author SHA1 Message Date
Matthias Koefferlein 7a26768d8a Updated testdata 2020-06-26 17:46:41 +02:00
Matthias Koefferlein 03dacbd2f5 Updated testdata 2020-06-26 17:46:39 +02:00
Matthias Koefferlein d141c0895d Added tests for Region's andnot. 2020-06-14 18:12:17 +02:00
Matthias Koefferlein 41fe04bbc8 WIP: twobool local processor 2020-06-14 17:00:54 +02:00
Matthias Koefferlein 4390a80dda Added test cases for multiple-outputs local processors. 2020-06-13 23:57:40 +02:00
Matthias Köfferlein 2d0a9418f9
Implemented #579 (perimeter_only mode for antenna check) (#582) 
* WIP: added basic feature and tests.

* WIP: provide tests are GSI binding of new antenna check

* Fixed issue #579 (perimeter_only mode for antenna check)

* Updated DRC doc for 'perimeter_only'
 2020-06-05 10:55:07 +02:00
Matthias Koefferlein 156e325e71 Updated unit test golden data 2020-05-31 02:12:00 +02:00
Matthias Köfferlein 6601d472bf
Implemented #570 (perimeter included in antenna check) (#572) 
* First implementation of the perimeter factor for antenna check, unit tests.

* Bugfix and unit tests for GSI binding of new antenna check version.

* DRC integration of perimeter-enabled antenna check.

* Enhanced DRC doc for antenna rule
 2020-05-30 21:45:48 +02:00
Matthias Köfferlein 3246e0d36f
Fixed #565 (SPICE global nets must not produce pins if not present) (#567) 
* Fixed #565 (SPICE global nets must not produce pins if not present)

* Fixed unit tests.
 2020-05-26 23:47:59 +02:00
Matthias Koefferlein b84a9df2da Persisting texts now for .l2n format 2020-05-22 00:58:46 +02:00
Matthias Koefferlein c682cc85d0 Generalized concept of region, texts etc. into 'shape collections'. Fixed LVS and DRC tests. 2020-05-21 23:59:30 +02:00
Matthias Koefferlein 854320d52d Debugging: proper assignment of net names through labels. 2020-05-20 23:27:06 +02:00
Matthias Koefferlein e9af72ee28 Tests for texts as net names, fixed Shapes test (order of texts) 2020-05-20 01:05:19 +02:00
Matthias Koefferlein 7dab87b881 Added tests, Region#pull_interacting with texts 2020-05-15 23:48:21 +02:00
Matthias Koefferlein 16d6c75b0e Fixed build, added tests for filter in deep texts object. 2020-05-13 17:58:00 +02:00
Matthias Koefferlein 4e7d0a81b8 'interact' between regions and texts. 2020-05-13 17:29:10 +02:00
Matthias Koefferlein c1b1ce6951 Provide unit test for DeepTexts. 2020-05-12 21:43:11 +02:00
Matthias Köfferlein 9b0362d03d
Fixed #544 (ignore duplicate global nets in SPICE reader) (#545) 2020-04-26 16:54:13 +02:00
Matthias Koefferlein c640347570 MERGE: added Spice reader testcase for resistors with model names. 2020-04-01 23:19:21 +02:00
Matthias Koefferlein b35429291e WIP: join_nets implemented, join_symmetric_nets: enhanced detection of symmetric nets. 2020-02-27 00:52:03 +01:00
Matthias Köfferlein 6a996b6f5b
Merge pull request #465 from KLayout/issue-462 
Implemented #462 (Generalize MOS transistor extraction to other gate …
 2020-01-05 01:02:54 +01:00
Matthias Koefferlein 811560094a Updated tests. 2020-01-04 21:19:06 +01:00
Matthias Koefferlein 833edf53b2 Implemented #462 (Generalize MOS transistor extraction to other gate figures) 2020-01-02 22:20:45 +01:00
Matthias Koefferlein 6a47437702 Updated test data. 2019-12-18 17:28:46 +01:00
Matthias Koefferlein 3441070908 Merge branch 'issue-448' into dvb 2019-12-15 23:57:42 +01:00
Matthias Koefferlein 3e32ca1ada Updated test data for Windows. 2019-12-15 23:54:17 +01:00
Matthias Koefferlein 12c040aa6c Merge branch 'issue-448' into dvb 2019-12-15 20:51:35 +01:00
Matthias Koefferlein b802220ae9 Updated test data 2019-12-15 10:48:11 +01:00
Matthias Koefferlein fccd78a222 Fixed #448 and updated test data 2019-12-15 10:37:51 +01:00
Matthias Koefferlein 06a68b77d2 Updated test data for windows. 2019-12-15 10:17:10 +01:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein 07daed2878 WIP: further updates of test data. 2019-12-15 00:24:17 +01:00
Matthias Koefferlein 96e591cba9 WIP: further updates of test data. 2019-12-15 00:23:05 +01:00
Matthias Koefferlein da1ac3661f WIP: bugfix of refactoriung, update test data. 2019-12-15 00:16:47 +01:00
Matthias Koefferlein 07a85e3ec3 Added test data. 2019-12-09 21:40:24 +01:00
Matthias Koefferlein 3b9beb0d49 Fixed #438 (error on redefinition of subcircuit in SPICE) 2019-12-07 23:39:39 +01:00
Matthias Koefferlein 64bb01d80d Dropped attempt to remove dummy nodes from spice reader netlist as this wasn't effective anyway. 2019-11-24 00:23:19 +01:00
Matthias Koefferlein 1a92bae3a8 Another update of golden data. 2019-11-23 23:38:38 +01:00
Matthias Koefferlein ed00503d41 Fixed Spice reader: must not use Netlist::purge_nets to remove dummy nets. Updated golden test data. 2019-11-23 23:36:52 +01:00
Matthias Koefferlein 1309aa59cb Merge branch 'master' into issue-425 2019-11-23 01:55:28 +01:00
Matthias Koefferlein dd7309ee9d Added missing test file. 2019-11-23 01:23:41 +01:00
Matthias Koefferlein 18b80489ed Added test data. 2019-11-23 01:20:59 +01:00
Matthias Koefferlein 2757b22da6 Resolved conflicts for issue-419 merge 2019-11-22 23:34:03 +01:00
Matthias Köfferlein ac7e17ffcb
Merge pull request #422 from KLayout/issue-406 
Issue 406
 2019-11-22 23:12:16 +01:00
Matthias Köfferlein c8cf8122b6
Merge pull request #414 from KLayout/issue-411 
Issue 411
 2019-11-22 23:11:24 +01:00
Matthias Koefferlein 6648b53822 Fixed issue #419 (multiple top circuits after flatten of netlist) 
The problem is solved by always producing subcircuits for cell
instances, even if there are no connections.

The netlist comparer had to be adjusted too because subcircuits
without pins were used for representing "unknown" subcircuit pairing.

In addition, this patch should lead to a better matching of
parallel subcircuit configurations where two different subcircuits
are entirely parallel.
 2019-11-20 21:56:12 +01:00
Matthias Koefferlein 6c7ceb74dc Enhanced intersections algorithm so that the generated points won't overlay with finite edges from the AND part 2019-11-19 21:19:36 +01:00
Matthias Koefferlein 990961e5f4 Fixed #411 (multiple device extractors for same class) 2019-11-17 23:12:50 +01:00
Matthias Koefferlein 8dddc4000f Also write the net properties to GDS or OASIS 
"build_nets" will now write the net's properties
to the generated net shapes.
This might enable interesting applications.
 2019-11-13 23:09:09 +01:00
Matthias Koefferlein 7309688944 More robustness of snap algorithm for unit tests 2019-11-12 20:13:35 +01:00
Matthias Koefferlein 86e041cd51 Updated test data. 2019-11-11 23:03:40 +01:00
Matthias Koefferlein 4a212e8db6 Added tests for Region#scale_and_snap and Region#snap 2019-11-07 23:33:54 +01:00
Matthias Koefferlein 988b1e563f Added unit test for DeepRegion::snap 2019-11-07 23:11:34 +01:00
Matthias Koefferlein 318efbf7b0 Fixed 'scale_and_snap' feature 2019-11-07 22:54:16 +01:00
Matthias Koefferlein 4924d0269c Fixed #400, added tests. 2019-11-06 23:28:16 +01:00
Matthias Koefferlein c8aa926fb0 Another update of testdata for MSVC 2019-11-03 09:07:00 +01:00
Matthias Koefferlein 3dffe91f88 Attempt to fix testdata for MSVC 2019-11-03 02:30:52 +01:00
Matthias Koefferlein 7910ddc6a3 Fixed a compiler warning, testcase update (part 1) 2019-11-02 20:39:59 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein 2325e1bce4 Merge branch 'dvb' into pull_feature 2019-10-04 22:58:52 +02:00
Matthias Koefferlein e1d77a1476 pull_interacting for edges/edges and edges/regions, some enhancements and bug fixes 
Bug fixes:
- use dist 1 to cover touching case properly in local processor
- handling of raw mode and is_merged state

Additional tests
 2019-10-03 13:08:37 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein cd137e6b3e Another fix for MSVC golden data. 2019-08-30 14:24:07 +02:00
Matthias Koefferlein ab66186db4 Updated MSVC test golden data 2019-08-30 13:03:37 +02:00
Matthias Koefferlein 5cfadad54f Updated test data. 2019-08-30 11:01:00 +02:00
Matthias Koefferlein 2a8f4c9610 Updated test data. 2019-08-30 10:52:51 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein 45cdefcf9a Provide strict mode for device classes, dmos3/dmos4 for LVS 2019-08-20 23:12:17 +02:00
Matthias Koefferlein b7c83eaaa6 Spice reader: subcircuits w/o pins 
This happens for subcircuits which only
connect to global nets.

Plus: ".global" now accepts more than just one net
 2019-08-19 23:00:24 +02:00
Matthias Koefferlein 1bc03c3b79 Implement "M" parameter for Spice 
This implementation is pretty simplistic and
applies "M" the following way:
* R: R(final) = R/M
* L: L(final) = L/M
* C: C(final) = C*M
* M: W(final) = W*M
* D: A(final) = A*M
* Q: AE(final) = AE*M

The other parameters (specifically the other
geometry parameters) are not scaled yet.
 2019-08-19 22:51:22 +02:00
Matthias Koefferlein 24b985f32e Better .include for Spice reader 
* .inc is allowed as synonym
* Paths can be URL's (with HTTP)
* Relative resolution of paths/URL's vs. parent of .include
 2019-08-19 21:45:40 +02:00
Matthias Koefferlein 4cee051255 Another update of golden test data (MSVC) 2019-07-27 22:31:01 +02:00
Matthias Koefferlein 71f646c24f WIP: updated test data for latest updates, don't sort LVSDB on reading for consistency 2019-07-27 21:42:51 +02:00
Matthias Koefferlein b4fa4b1bae Flattening of layout with circuit flattening. 
Technically, the layout isn't flattened, but connections are made
which allow regenerating the layout even after the circuit
has been flattened.
 2019-07-27 00:37:22 +02:00
Matthias Koefferlein 14d9689498 Added .global to Spice reader. 2019-07-22 23:02:31 +02:00
Matthias Koefferlein e5852a7757 Updated alternative golden test data for Windows too 2019-07-19 00:14:57 +02:00
Matthias Koefferlein 0215d05a12 Fixed unit tests. 2019-07-19 00:02:05 +02:00
Matthias Köfferlein 142085bd64 Provide new golden data for two test for Windows. 2019-07-16 23:50:52 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein ca6d05d3c1 Updated tests 2019-07-12 00:22:45 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 621c3f74ed WIP: reader delegate - GSI binding, tests. 2019-06-22 22:03:32 +02:00
Matthias Koefferlein 343e340e22 WIP: SPICE reader delegate, unit tests + debugging 2019-06-22 19:44:33 +02:00
Matthias Koefferlein d174fb73fd WIP: preparations for SPICE reader delegate. 2019-06-22 18:37:32 +02:00
Matthias Koefferlein 46dafd50ea WIP: unit tests updated 2019-06-22 10:15:32 +02:00
Matthias Koefferlein 9647c94c68 WIP: added NE parameter for BJT3/4, AE and NE are primary parameters now. 2019-06-21 23:41:08 +02:00
Matthias Koefferlein b521269805 Added missing test case files. 2019-06-18 01:56:46 +02:00
Matthias Koefferlein e939d51104 WIP: BJT4 device, more parameters for resistor (W,L), BJT devices for Spice writer, tests updated 2019-06-15 18:22:04 +02:00
Matthias Koefferlein 1b2a611d83 WIP: diode extraction test. 2019-06-15 09:34:04 +02:00
Matthias Koefferlein 0b5db06ca8 WIP: tests for BJT extraction 2019-06-14 23:45:04 +02:00
Matthias Koefferlein 4212a783a5 WIP: test cases for device extractors R/C with bulk 2019-06-14 21:21:11 +02:00
Matthias Koefferlein dd63d55304 Updated test data 2019-06-13 13:40:57 +02:00
Matthias Koefferlein 0d623bc57a Avoid netlist extraction issues with duplicate instances 
So far, duplicate instances have lead to net propagation
into parent cells and floating nets. This is fixed by ignoring
duplicate instances where possible.
 2019-06-13 13:33:28 +02:00
Matthias Koefferlein 8e1dadbe59 Updated golden data of unit tests. 2019-06-13 09:02:47 +02:00
Matthias Koefferlein ebd00c186b Enhancements for net export feature 
- some refactoring
- better performance (was slow because layer iteration
  was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
  produced. For this a new argument is added to
  LayoutToNetlist::create_cell_mapping (nets) which
  allows selecting the nets for which a cell mapping
  is requested
 2019-06-12 22:55:24 +02:00
Matthias Koefferlein 0f666d528c Updated golden data for MSVC 2019-06-11 23:38:58 +02:00
Matthias Koefferlein 93be648ee1 Updated golden data for MSVC 2019-06-11 21:37:23 +02:00
Matthias Koefferlein 7d6237a90a Unescaping of net names on Spice reader -> writer/reader should be self-compatible. 2019-05-31 22:55:09 +02:00
Matthias Koefferlein 985cffc099 Unique net names for Spice netlist writer 2019-05-31 22:19:51 +02:00
Matthias Koefferlein c684633dd6 Some enhancements for netlist extraction and writer 
* Spice writer can now be configure to skip the debug
  comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
 2019-05-31 00:11:28 +02:00
Matthias Koefferlein 1764ce04af Special golden data for MSVC/dev ex test 2019-05-29 23:37:50 +02:00
Matthias Koefferlein 9bf1263efa Special golden data for MSVC/LVS test 2019-05-29 23:34:55 +02:00
Matthias Koefferlein 1935ee7ff9 Tried to fix unit tests for MSVC 2019-05-29 22:09:39 +02:00
Matthias Koefferlein dea2b76dc8 Added unit tests for res and cap device extractors. 2019-05-29 21:35:02 +02:00
Matthias Koefferlein 10667d8e35 Bugfixed last commit, fixed unit tests. 2019-05-29 00:51:42 +02:00
Matthias Koefferlein f8646412ca Added missing files 2019-05-25 01:19:32 +02:00
Matthias Koefferlein 252622e3f8 Fixed unit tests, support floating pins for netlist compare 2019-05-20 23:48:07 +02:00
Matthias Koefferlein 625b173379 Reworked l2n and lvsdb format such that reading/writing gets more reproducible: maintain unnamed state of devices, subcircuits and pins 2019-05-20 22:33:23 +02:00
Matthias Koefferlein 834dcc7474 WIP: LVSDB reader/writer fixes 2019-05-19 23:42:31 +02:00
Matthias Koefferlein ea8320dcf8 WIP: LVSDB reader/writer: bugfixes, refactoring, tests. 2019-05-19 22:55:03 +02:00
Matthias Koefferlein ea28530c55 L2N: combined device persistance (complex concept - needs simplification?) 2019-05-10 00:15:51 +02:00
Matthias Koefferlein c33fd40ec9 Switched l2n format to relative mode by default (relative mode is an option and maybe shorter) 2019-05-04 23:06:18 +02:00
Matthias Koefferlein 548f16f1df WIP: tried to provide a more consistent net building feature (here: building hierarchical nets with properties as net annotation - needs cell variants if properties are assigned to subcells too) 2019-05-04 00:37:38 +02:00
Matthias Koefferlein 2aaec56adb WIP: netlist browser - extended the net export scheme of build_net to support net annotation and flattening. 2019-05-03 23:33:37 +02:00
Matthias Koefferlein e661bac0a7 Netlist browser: fixed a segfault on 'unload all' 2019-04-28 22:57:06 +02:00
Matthias Koefferlein 7f9da5e8de Introduced concept of device class templates 
This concept allows to persist at least the standard
(built-in) device classes into L2N DB files. This way
device classes are persisted.
 2019-04-23 19:44:07 +02:00
Matthias Koefferlein f6836b96a2 WIP: some enhancements 
Spice writer: don't prefix model name with "M"
Added "device_class_mismatch" message to netlist compare
Assertion if device classes or circuits are nil on
"same_..."
 2019-04-07 10:15:57 +02:00
Matthias Koefferlein 52fb8b0f65 Merge remote-tracking branch 'remotes/origin/master' into dvb 2019-04-04 07:35:43 +02:00
Matthias Koefferlein 89ffd7e3da WIP: Simple SPICE reader. 2019-04-01 22:46:33 +02:00
Matthias Koefferlein 9613ad72c8 WIP: netlist compare - using it for more tests 
Issue solved: some circuit pins may not have a net - these
need to be ignored.

Requirement: all pins with a net must be mapped.

Detached pins are not present in the mapping table.
A dummy mapping table was introduced to allow dropping
of pins in the second circuit too.

Output of compare should not depend on memory location
anymore and pin mismatch reporting should include all
pins.
 2019-03-31 23:59:43 +02:00
Matthias Koefferlein e545d6af3f Refined solution for issue-245 by providing a better name mapping (checked with ngspice) 2019-03-22 00:05:17 +01:00
Matthias Koefferlein 9356f32026 Fixed issue-245 (support Spice netlist with names instead of numbers) 
The option is in the Spice writer (writer.use_net_names=true).
 2019-03-21 23:34:16 +01:00
Matthias Koefferlein ab8107de2d Bugfix: Spice writer needs 'P' suffix for source/drain area of MOS 2019-03-10 01:26:52 +01:00
Matthias Koefferlein 8b29b30ff9 WIP: more consistent text handling 
Texts are not only kept inside original layers, but
also inside deep layers. This enables using texts
from DRC.

However, texts in deep layers are kept as markers.
Mostly they are converted back to texts, but the
orientation will be lost.

The change eliminates the need to using Iterators
in DRC instead of original layers and use of
label layers in deep mode.

A drawback is the presence of marker shapes in
deep mode (unless polygon layers are created).
Also, text output to RDB is not supported from
deep layers currently.
 2019-03-06 00:34:56 +01:00
Matthias Koefferlein bacd565d05 Bugfix: Spice writer added one pin too much to MOS4 transistors. 2019-03-04 17:26:35 +01:00
Matthias Koefferlein 8d3b94201e Antenna check: tests added, 'catchall' diode protection 2019-03-01 23:07:28 +01:00
Matthias Koefferlein 9f4f2d58d7 First version of antenna check. 2019-02-28 23:56:49 +01:00
Matthias Koefferlein d4ed21f42a Just new tests 2019-02-25 22:34:06 +01:00
Matthias Koefferlein 3c6aafcc0c Region: hierarchical text object detection implementated. 2019-02-23 00:56:55 +01:00
Matthias Koefferlein 18f74bac1e Enabled transformations for deep regions/edges/edge pairs - important for handling layouts with different DBUs in DRC 2019-02-22 01:02:48 +01:00
Matthias Koefferlein 91407ddaa9 Added tests for region processors. 2019-02-20 21:40:43 +01:00
Matthias Koefferlein 496b695ef0 Refactoring of the polygon processing in Region 2019-02-19 22:11:55 +01:00
Matthias Koefferlein 9ec6b44c93 Added some tests for the previous commit. 2019-02-18 00:15:26 +01:00
Matthias Koefferlein 311318c578 Ported edge/edge DRC functions to hierarchical mode. 2019-02-17 18:54:33 +01:00
Matthias Koefferlein c40f147dc7 Edge/edge and edge/polygon interaction test ported to hierarchical mode. 2019-02-17 18:36:15 +01:00
Matthias Koefferlein 7ef0451ca8 Partial segments of edges converted to hierarchical operations. 2019-02-17 17:53:21 +01:00
Matthias Koefferlein 74006b6208 Hierarchical implementation of extended method for edges 2019-02-17 17:34:31 +01:00
Matthias Koefferlein ae783a2245 Hiearchical implementation of edge filter. 2019-02-17 16:18:24 +01:00
Matthias Koefferlein 61d766bd4c Hierarchical implementation of edge to region operations. 2019-02-17 16:05:39 +01:00
Matthias Koefferlein e6ee1c064e Hierarchical implementation of edge/edge booleans. 2019-02-17 15:07:16 +01:00
Matthias Koefferlein 8e5bffcf18 Hierarchical angle check. 2019-02-17 11:42:30 +01:00
Matthias Koefferlein a7bfaac424 Cell variant resolution by propagation, grid check now implementation hierarchically (with propagation) 2019-02-17 10:59:04 +01:00
Matthias Koefferlein 6e35e80963 Hierarchical implementation of polygon vs. edge interact 2019-02-15 23:43:45 +01:00
Matthias Koefferlein 78617930dd Hierarchical implementation of self-overlap merge. 2019-02-13 22:41:12 +01:00
Matthias Koefferlein ddcfda8761 Some optimization: keep merged state in deep region. 2019-02-13 17:17:03 +01:00
Matthias Koefferlein 68947bedd2 Updated golden test data. 2019-02-13 01:11:15 +01:00
Matthias Koefferlein b0fc2be96e Deep regions: some more operations implemented hierarchically 
- snap (!) - but only for gx == gy
- filtering
- interact/inside/outside/overlap + not_... variants
- edges
 2019-02-13 01:07:32 +01:00