mirror of https://github.com/KLayout/klayout.git
Updated tests
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@ -112,6 +112,9 @@ device(D$NMOS$1 NMOS
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INV2
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# Circuit boundary
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rect(-1700 -1640 1400 4580)
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# Nets with their geometries
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net(1
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rect(nwell -1400 1800 1400 4580)
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@ -252,6 +255,9 @@ circuit(INV2
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)
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circuit(INV2PAIR
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# Circuit boundary
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rect(0 -840 5740 5380)
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# Nets with their geometries
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net(1 name(BULK))
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net(2
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@ -334,6 +340,9 @@ circuit(INV2PAIR
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)
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circuit(RINGO
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# Circuit boundary
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rect(-1720 -1640 25160 4580)
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# Nets with their geometries
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net(1 name(FB)
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rect(diff_cont 22850 2490 23070 2710)
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@ -763,10 +763,10 @@ match_devices $1 $2
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end_circuit INV INVB MATCH
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begin_circuit TOP TOP
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets IN IN
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match_nets VSS VSS
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match_nets INT INT
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match_nets IN IN
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match_nets VDD VDD
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match_pins $0 $2
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match_pins $1 $0
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match_pins $2 $1
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@ -839,12 +839,12 @@ match_devices $3 $3
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match_devices $4 $4
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end_circuit NAND NAND MATCH
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begin_circuit TOP TOP
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match_nets IN2 IN2
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match_nets INT INT
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match_nets IN1 IN1
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets VDD VDD
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match_nets INT INT
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match_nets IN2 IN2
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match_nets IN1 IN1
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match_pins $0 $0
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match_pins $1 $1
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match_pins $2 $2
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@ -883,12 +883,12 @@ match_devices $3 $3
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match_devices $4 $4
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end_circuit NAND NAND MATCH
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begin_circuit TOP TOP
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match_nets IN2 IN2
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match_nets INT INT
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match_nets IN1 IN1
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match_nets OUT OUT
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match_nets VDD VDD
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match_nets VSS VSS
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match_nets VDD VDD
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match_nets INT INT
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match_nets IN2 IN2
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match_nets IN1 IN1
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match_pins $0 $0
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match_pins $1 $1
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match_pins $2 $2
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