535ef6be38
Change function return value from Verilog_Result to <funcname>_Result
2008-08-21 19:44:12 +01:00
c404b761b7
Change `out' ports to `buffer' when the signal is read
...
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
2008-08-11 20:48:28 +01:00
7ed8c0915d
Add file/line comments to signal declarations
2008-08-08 20:28:16 +01:00
090ae5fa56
Catch case where signal with same name in task and module
...
This fixes task3.14C
2008-08-08 19:47:20 +01:00
13cb81f4bb
Add task signals to containing architecture
...
This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
bb0efda526
Make make_safe_name case insensitive
2008-08-07 17:58:42 +01:00
49a2693357
Add file / line number information to functions
2008-08-03 14:46:57 +01:00
10a5ca199d
Add file / line number comments to instantiations
2008-08-03 14:38:08 +01:00
c2f622327f
Use ivl_scope_def_* for definition file/line numbers
2008-08-03 14:34:41 +01:00
45dfa28dba
Remember signal pin a nexus was attached to
...
Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
c8cbac58f5
Add forward declarations for functions
...
This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
5d0df8d880
Change format of line file/line numbers
2008-08-02 10:42:00 +01:00
bb80b432e6
Add comments file/line number comments
...
Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
baa2363e85
Split logic device code into separate file
2008-07-30 10:13:08 +01:00
e5b8abfb23
Remove debugging output
2008-07-29 21:15:51 +01:00
9a5b7bb0b0
Connect signals together if joined in a nexus
2008-07-29 21:03:00 +01:00
eaf1cc9120
Fix assertion failure with arrayed signals
2008-07-29 19:47:17 +01:00
3bcd42dc8f
Fix case where logic device has no valid output
2008-07-29 19:39:20 +01:00
744fbed783
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
c9454b346e
Fix module3.12B
2008-07-29 19:04:41 +01:00
5ec2c37e7e
Get functions working again
2008-07-29 15:29:49 +01:00
25602e487d
Comment
2008-07-29 15:12:51 +01:00
e037ffd952
Create temporaries for LPM outputs
2008-07-29 15:09:58 +01:00
48c1a7982c
Make seen_nexus private
2008-07-29 14:24:04 +01:00
a842b327c7
Generate constant drivers as concurrent assignments
2008-07-29 14:02:05 +01:00
f8034d69ef
Fix constants in nexuses
2008-07-29 13:30:54 +01:00
680c6f0503
Make sure LPMs have valid inputs/outputs
2008-07-29 13:06:21 +01:00
39717989a8
Call set_active_entity in the right places
2008-07-29 13:04:29 +01:00
c26b7ce675
Port maps
2008-07-29 13:02:55 +01:00
c6f6ea7358
Instantiation working again
2008-07-29 12:21:19 +01:00
c0c838f1bc
Logic devices now working again
2008-07-29 12:11:44 +01:00
1a45e9164f
Find signal a logic device is connected to
2008-07-29 12:04:40 +01:00
8a5f129e56
Draw nexus in multiple passes
2008-07-29 12:00:26 +01:00
65c2ceb89d
Build entity hierarchy in separate stages
2008-07-29 11:01:02 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
30fdadc525
Support delays in logic devices
2008-07-23 13:40:42 +01:00
2d79e1a2e0
Store the currently active entity
2008-07-19 14:45:00 +01:00
4d9f029000
Generate correct array bounds
2008-07-17 14:38:07 +01:00
1d3ac6bc1f
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
642fbe9fc5
Correct check for arrays
2008-07-17 11:31:06 +01:00
f3753ea9ad
Add warning that arrays are not yet implemented
2008-07-15 18:09:18 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
65720f49fe
Simple bufif cases
2008-07-14 19:00:58 +01:00
6243736481
Pull-up/pull-down logic devices
2008-07-14 12:04:20 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
78ee61558d
Remove redundant test
...
Signal is guaranteed to appear in arch_scope or its parent
by the surrounding `if' statement.
2008-07-13 15:27:07 +01:00
07c4ff7ea7
Add assertion about result of lpm_to_expr
2008-07-13 15:26:03 +01:00
e5422dddd2
Remove useless `ignore' param to nexus_to_expr
2008-07-13 15:24:35 +01:00
6af201ea03
Refactor nexus expansion functions.
...
Now a single function nexus_to_expr
2008-07-13 15:17:14 +01:00
27a40cfdcd
Constant assignments to outputs
...
If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
2008-07-13 13:02:17 +01:00
3bd480a375
Allow ouput to be read if connected to child output
...
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
37fe6e4219
Dummy implementation of IVL_LO_BUF*
2008-07-07 15:49:51 +01:00
4db5b9d7ed
Add unary OR/NOR
...
These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
dadd145d09
Add message for unsupported LPM nexus pointer
2008-07-07 15:04:28 +01:00
c33600bcc3
Add concatenation operator
2008-07-06 18:21:34 +01:00
3d0a2b55ce
Avoid declaring same function multiple times
...
If it appears in multiple places in the hierarchy
2008-07-04 12:03:37 +01:00
dbbadbc309
Make sure the renamed signal is used in the sensitivity list
2008-07-03 16:13:02 +01:00
fb08164cbc
List some more illegal VHDL names
2008-07-03 15:20:43 +01:00
7e999c5496
Fix continuous assignment of constants
...
E.g. in assign p = 1 the RHS signal in the generated LPM now
has a correct intial value (and it will never be written to
elsewhere)
2008-07-03 15:13:12 +01:00
35c66744db
Cleanup and remove debug output
2008-07-01 11:31:00 +01:00
930e04f6c7
Ensure port map expressions are globally static
2008-07-01 11:28:02 +01:00
37756b8d06
Avoid mapping a signal to itself
2008-07-01 11:13:02 +01:00
596c93ce7e
Rename instance if it has the same name as the type
2008-07-01 11:05:24 +01:00
624943b3ca
Simplify port map generation code
2008-07-01 10:59:31 +01:00
ef89a760d6
Add vhdl_element::print method for debugging
2008-07-01 10:44:20 +01:00
f03dfb50ad
Refactor nexus_to_var_ref
2008-07-01 10:33:46 +01:00
4e73b1b133
Fix bug when resolving nexus to VHDL signal
2008-06-30 17:47:45 +01:00
b82ca28190
Add XOR logic type and fix part select
2008-06-30 16:18:55 +01:00
f800298d01
Fix memory leak
2008-06-27 12:29:50 +01:00
301a25303f
Remove useless assertion
2008-06-27 12:21:53 +01:00
b24eb6ce88
Handle local variables in functions
2008-06-27 12:21:27 +01:00
fd60bfd3d2
Rewrite function parameter finding code
2008-06-27 12:18:39 +01:00
500442e5c5
Working function calls
2008-06-25 22:15:57 +01:00
d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
7773000c36
Generate function declarations
2008-06-25 21:40:35 +01:00
042f7ccbcd
Generate a return type for functions
2008-06-25 18:43:50 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
43c671cb5c
Emit VHDL for function declarations
2008-06-25 18:00:48 +01:00
c01c2bd742
Dummy code for handling function scopes
2008-06-25 12:48:46 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
08d80b35cb
Rename signals that would be illegal VHDL names
2008-06-19 16:15:47 +01:00
561953e494
Minial LPM to support continuous assignments
2008-06-16 19:41:01 +01:00
83a7796b74
Make sure signal names conform to VHDL rules
2008-06-16 17:37:17 +01:00
2fb57805ea
Use signed rather than std_logic_vector
...
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
005df31a0d
Use renamed signal in expressions, if there is one
2008-06-13 12:39:18 +01:00
d6193c1622
Add _Reg internal signal if output is registered
2008-06-13 12:34:27 +01:00
26a2c69c2e
Change architecture name to `FromVerilog'
2008-06-11 11:31:43 +01:00
babe694366
Generate port mappings
2008-06-10 13:58:41 +01:00
7560b29fb9
Find signals to map together
2008-06-10 12:21:48 +01:00
3106fe0ed6
Generate port declarations for entities.
...
But doesn't emit them yet!
2008-06-09 16:27:04 +01:00
e29954e03f
Generate concurrent assignments from logic gates
2008-06-09 15:05:32 +01:00
3b5d56e087
Allow n-ary expressions
2008-06-09 14:53:50 +01:00
Nick Gasson