This patch adds the ability to call a system function as a task for
the SystemVerilog generation (-g2009). The return value is really
calculated, but it is ignored.
This patch adds support for a UDP with variable delays. In the process the
intrinsic support for delays was removed from the UDP functor and replaced
with a call to the .delay functor. Both a normal gate and a UDP now use the
same code to generate the delay.
This patch adds checks that the delay count is correct for the
various gates and adds support for a missing variable decay
time. For this case the decay time is the minimum of the rise
and fall times. This is denoted by setting the decay variable
to 0 in the vvp file. vvp notes this and sets an ignore decay
time property in the base delay. This turns off the ability
to set the decay time and the minimum delay calculation will
also update the decay time.
This patch pushes delays for tranif gates to the code generator.
We still need to add checks for the number of delays, etc. For
now an error message is printed when a tranif gate is given a
non-zero delay.
Elaborate conditional assignments with BUFZ devices that do *NOT*
preserve strengths. Add a BUFT (transparent) device that can be
used in those cases where I really need a transparent buffer.
A real delay must be scaled and rounded using the local precision
before it is finally scaled to the simulation time units. This
patch fixes the compiler to do this correctly or generate the
correct code for run time calculated delays. Delays in a CA
already worked correctly. The run time was also fixed to scale
modpath (SDF back annotation) delays correctly.
Some new shadow issues have crept in. This patch fixes these new
issues and adds -Wshadow to the normal warning flags to keep any
new occurrences from happening.
The repeat expression is evaluated in a self determined context
(expression width == -1). It needs to call probe_expr_width() to
figure out the width needed by the expression before calling
elab_and_eval() to elaborate the expression.
This patch adds support for converting bit based ports to real signals.
You can only do this for single instances. Arrayed instance would
create multiple instances driving the same real signal.
Any real port can be connected to a bit based signal. The only limitation
is that the signal width must be an integer multiple of the instance
count since all the real conversions must have the same width.
Also add an error message for an arrayed instance with real to real
output connections. Again multiple drivers.
This patch also adds errors for inout real and bit based inout ports
driving a real signal. There is no logical way to deal with the full
capabilities of inout and real ports/signals. So for now they are not
allowed.
This patch cleans up some style issues: no need to check that a value
is defined before freeing or deleting it, use C++ style casts, make
sure to NULL terminate strncpy(), empty() is faster than size() for
size == 0 or size >= 0 checks, re-scope some variables, etc.
A named event does not have an edge so taking a posedge or negedge
is illegal. This patch adds an error message for this. Before the
edge was being ignored for named events, but this is incompatible
with other tools.
Creation of implicit nets requires knowledge of whether an identifier
has been declared before it is used. Currently implicit nets are
created during elaboration, but by this stage the order of declaration
and use is not known. This patch moves the creation of implicit nets
into the parser stage.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but for this directory we
mas as well remove the warnings we can. It also does not
recognize that an assert(0) or assert(false) ends a routine so
it complains about no return at end of function or variables
not being defined.
Currently the compiler only applies defparam statements that are
found in the initial root module hierarchy. This patch ensures that
defparam statements within scopes created by generate constructs or
instance arrays are also applied.
This patch is based on one from "bruce <bruce1914@gmail.com>".
I've applied all but the elaboration code, which I rewrote to
properly work with the elaboration work queue. I also constrained
the implementation so that the parameter name must have exactly
two components: the root scope name and the parameter name. This
is necessary to keep the defparm processing sane. The comments
from bruce's original patch are as follows:
--
This patch would provide function to define parameter from command
line. This serves the same functionality as 'defparam' in Verilog
source code, but provide much more ease for using. Parameter
definition can be write in command file, with following syntax:
+parameter+<scope>.<parameter>=<val>
*Do not apply any space between them*
The scope name should be full hierachical name with root name at
the begining. The following example would override test.T1 with
new value 2'b01:
+parameter+test.T1=2'b01
'test' here is the root module name. The parameter value here
should be constant. Parameter definition can also be write in
the command line:
iverilog -Ptest.T1=2'b01
This serves the same functionality with the previous example.
If we define the same parameter in command file and command line,
the one in command line would over-write all others.
This patch cleans up some unneeded code. Releases some allocated
memory before the compiler quits and fixes a couple minor memory
leaks in the compiler and vvp code generator.
Icarus has recognized this directive, but it did not do anything
with the information. This patch adds the functionality for most
common cases. It adds this by changing the input net type from
wire/tri to tri1 or tri0 depending on the pull. The issue is that
if the input net is not a wire or tri this is not safe and should
really be done as an external pull gate connected to the input.
We will need to handle this is it ever comes up. For now a sorry
message is printed.
This patch add code to print a warning message if it finds both a
default and `timescale based delays. The -Wall or more specifically
the -Wtimescale flag can be used to find the module with the missing
`timescale directive.
When a PGAssign is driven by (r-value) a bit, part or indexed
select and the strength is not the default (supply). Then
we need to create a driver (BUFZ) to convey the strength
information.
This patch adds messages in various places to warn that constant
user functions are not supported. It uses a global variable to
indicate when we are in a constant context. This is a bit of a
kludge, but works well without needing to change a bunch of code.
It is interesting to note that ports are elaborated late enough
that if we had the constant function evaluation code they would
evaluate correctly. This also applies to the function return
range, the concatenation repeat, specparams and initial values.
Signal definitions are early enough that elaboration is what is
failing because the function body is not available (has not been
elaborated). The same thing applies to both parameters and
localparms.
elaborate.cc:2456: warning: suggest parentheses around comparison in operand of &
vpi/vcd_priv.c:210: warning: operation on 'idx' may be undefined
Probable behavior change. Passes testsuite.
Functions that appear in continuous assignment expressions and that
have hidden dependencies or side effects need to be re-evaluated
whenever any input to the expression changes. This patch adds support
in the compiler and vvp runtime to enable this. This is currently
activated for any system function call that has no arguments. The
user may also force it to be used for any user function by passing
the option -gstrict-ca-eval to the compiler driver.
This patch also removes the -dautomatic option which was used for
gaining confidence in the code that supports automatic tasks and
functions. It is believed that the testsuite provides reasonable
fault coverage, and further tests can be added if bugs are found.
Probe the widths of the case statement expressions. The expressions
are self-determined in that context, but the probe is needed to
setup the expression types.
Verilog generate schemes support a special case where conditional
generate schemes that contain only a nested conditional generate
scheme do not create a new scope. Instead, it relies on the nested
generate scheme to generate the scope.
unary expressions that have problems should not assert in the
test_width method. Instead, let the error propagate back and be
handled during expression elaboration. This found a few places
where expression widths/types weren't probed before elaboration.
When padding a signal or when creating a local signal the file and
line information should be related to where the new object was
created not the signal value it is being created from.
This patch modifies the NetE* pad_to_width() routines to take a
LineInfo object to set the location to the correct value.
It fixes some set_line() calls to use the correct location.
It fixes ports to not set the file/line information if it is
already defined. Doing this was causing the definition of
signals to become the instantiation instead of the real
module declaration.
A simple typo in the rhs of an expression would crash the compiler.
Example:
module crash3;
reg clk;
integer cnt1=0;
always @(posedge clk) begin
cnt1 <= (cnt==81) ? 0 : (cnt1+1);
end
endmodule
This patch adds a number of compile and run-time checks for illegal
uses of variables declared in automatic tasks and functions. It
also adds a check for event expressions in automatic tasks that use
features not yet supported in VVP.
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.
This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.
This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.
While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
This fixes the sign calculation for port padding. It also reports if
the padding will be signed or not in the warning message. The inout
calculation may not be correct. It requires both the signal and the
port to be signed, but inout is not currently padded anyway.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
Later passes need the intermediate results for width and size so that
some special cases, were self-determined arguments occur, can be
processed properly during elaboration. This can be especially tricky
and interesting for ternary expressions.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.
This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
In assignments, the expression width may be defined by the width of
operands, and not that of the l-value. Choose whichever is creater and
set (or pad) the expression to that width.
This patch pads inputs and output ports correctly when the port
and the port expression have different widths. It does not fix
inout ports.
It also sets the file and line number information in the unsigned
pad_to_width() routine.
There are cases where the r-value doesn't pad itself to the width
that is requested by the call to elaborate_expr. This impacts the
elaboration of PGAssign. Pad/sign extend as appropreate.
Widths of real values are always 1. When paired with vectorable types
in expressions, the vectorable type is processed as losslessly self-
determined. ("unsized" in the test_width methods.)
the PGAssign elaborate method used the test_width to get the width
of the r-value expression. This should be completely sufficient to
get the width of the expression, so always use a defined width to
elaborate the expression.
It takes a carefully crafted source file to cause elabortion to make
an arrayed multiple-output gate that is not vectorized into a single
wide gate. But that special case does need to be handled.
Logic gates usually have one output and several inputs, but a few
have multiple outputs and one input. Since the NetNode objects have
only a single output, handle the case by creating multiple NetNode
objects, one for each output.
The r-value expression takes on at least the width of the l-value. If
there is a sized width greater then the l-value width, take that on
instead. But if the r-value is unsized, there are unsized sub-expressions
that cause the expression as a whole to be unlimited width, so elaborate
and evalulate the r-value as lossless.
This patch pushes the non-blocking event control information to
the code generator. It adds the %evctl statements that are used
to put the event control information into the special thread
event control registers. The signed version (%evctl/s) required
the implementation of %ix/getv/s to load a signed value into
an index register. It then adds %assign/wr/e event control based
non-blocking assignment for real values. It also fixes the other
non-blocking real assignments to use Transport instead of inertial
delays.
This patch adds blocking repeat event controls and also makes the
base repeat statement sign aware. If the argument to repeat is
negative (it must be a signed variable) then this is treated just
like an argument of 0 (there is no looping). Doing this allows us
to model the repeat event control as follows.
lhs = repeat(count) @(event) rhs;
is translated to:
begin
temp = rhs;
repeat (count) @(event);
lhs = temp;
end
This patch also pushes the non-blocking event control
information to the elaboration phase where it will report they
are not currently supported.
This patch moves the always zero or possibly zero delay checks
to a point after the circuit is full elaborated. Before it
could try to check tasks that had not already been evaluated
resulting in a crash.
In continuous assignment, the width of the expression needs to come
from the expression itself, and not just from the width of the l-value.
Use the PExpr::test_width method to get the width of the expression
to pass to the elaborate.
The expr:::synthesize methods need not deal with saturating left or
right shifts if they are dealt with early, in elaborate_expr methods.
So the elaborate_expr for shift takes on much more responsibility.
Because Icarus tries to elaborate as much as it can even after
an error has occurred we need to check for these errors during
elaboration. This patch prevent an undefined identifier from
crashing the compiler.
When the continuous assignment is signed, then sign-extend the r-value
in the few cases where the expression is stubbornly smaller then the
desired width.
When nets are assigned directly to a net, we need to create a driver
to carry the strength. Normally, the implied drive of a continuous
assignment is carried by whatever gate the r-value expression ends
with, but with simble net-to-net assignment, there is no net so we
need to install a BUFZ to carry the assignment.
convert the continuous assign elaboration to use elaborate_expr
and synthesize methods instead of the elaborate_net methods of
PExpr. This exposes problems with the synthesize methods, but it
is a better way to do it.
In preparation for using the synthesize method to replace the
elaborate_net method of PExpr, rework the interface to the
synthesize() method. This changes no fnctionality, but does set
up the infrastructure for the next step.
When driving an input port to a module, watch out for the case where
the net is also driven within the instance. If this is the case, take
pains to make sure what goes on in the instance doesn't leak out
through the input port. Add a BUFZ (continuous assignment) to isolate
the context from internal driving.
When generate schems and instance arrays are nested, it takes
multiple iterations of elaborate scope, defparams and evaluate
parameters before everything is worked out. Rework the work item
processing so that the loop elaborates scopes and runs defparams
in phases. The phases are needed so that we can tell when the
remaining defparams are orphaned.
Putting scope elaboration into work queue items allows for handling
more complex processing order. The elaboration_work_list queue drives
the processing of elaborate_scope and parameter evaluation.
This patch adds .cast/int and updates .cast/real to act as a local
(temporary) net and to support either a signed or unsigned input.
The vvp_vector4_t class not can convert an arbitrarily sized double
to a vector value. This removes the restriction of lround().
Also document the new statements.
Generating task/function definitions involves getting the functions
to put themselves into the generate scheme instead of the module,
and getting elaboration to elaborate those definitions in the
generate scheme.
Named begin/end blocks burried within generate schemes need to be
elaborated. Handle this by remembering to elaborate_scope on the
statements within the generate scheme.
In the process, clean up/regularize some of the member names and
methods.
Rather then join islands while branches are initially created, save the
island creating for the end. This way, the process is actually recursive
and greedy, reliably collecting branches into islands without conflict.
Fold the bi-directional part select into the pass switch (tran) support
so that it can be really bi-directional. This involves adding a new
tranvp device that does part select in tran islands, and reworking the
tran island resolution to handle non-identical nodes. This will be needed
for resistive tran devices anyhow.
NetTran devices must be collected into islands because they are all
a bi-directional mass. This is how vvp will process them and the code
generator will need a head start organizing them.
This involves defining the API for switches and cleaning up the
elaborated form to match the defined ivl_target API. Also add t-dll
code to support the ivl_switch_t functions, and add stub code that
checks the results.
The tran devices include tran, rtran, tranif0/1 and rtranif0/1. These
are all elaborated as options on a NetTran device. It is still not
clear the best way to present tran devices via the ivl_target.h API.
The elaborator improperly allowed user function call nodes to take on
the expression width requested of them. The result was that generated
code had junk pad bits in certain cases.
This patch adds code to push the file and line information
for scope objects (modules, functions, tasks, etc.) to the
runtime. For modules, this includes the definition fields.
This patch adds ifnone functionality. It does not produce an
error when both an ifnone and an unconditional simple module
path are given. For this case the ifnone delays are ignored.
Logical and/or take as inputs condition expressions, which are scalar
expressions. Be sure to reduce vectors using proper logic to get the
right condition value.
This patch adds check to determine if an always block has delay
in it or not. If there is no delay a runtime infinite loop will
occur. For the indeterminate case it will print a warning message
if the new -Winfloop flag is given. This flag is not part of the
-Wall check!
This patch uses the true delay expression count not the truncated
one to check that the number of delay expressions is correct.
It also prints the actual number of expressions it found when
printing the error message.
If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.
These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
When a bit port of a module instance is connected to a vector
argument, the MSB module instance should be connected to the MSB
of the vector argument. This matters only in the rare case that
the %m is used. It also makes wave dumps come out right.
Normally processes are found in the lexical scope of a module, but
there are special cases where processes (other then task/function
definitions) are in other lexical scopes. The most likely case is
initilizations that are in the lexical scope where the assigned
variable is declared.
In the process, the behaviors list is kept in the base PScope class
instead of the Module or any other derived lexical scope class.
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
Padding and continuous assignment caused problems if the continuous
assignment includes a delay. The problem is that the padding was
not necessarily included in the delay. Rework the elaboration to
make sure the padding is indeed included in the delay.
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
This patch causes unnamed generate blocks to be automatically named
using the naming scheme defined in the Verilog-2005 standard. This
is a fix for the problem discussed in pr1821610.
Here are some more array fixes. They are mostly better error messages
instead of just asserting and some code cleanup. The one new thing
that probably should have been a separate submission is that down
indexed part select [base -: width] can now be a lvalue.
@* was only expanding to input nets. nex_input() for blocks was removing
any output net that was also an input. There was also a bug in how output
nets were removed. Only outputs currently defined were removed from the
input list.
always @(*) begin
y = a;
z = y;
end
would report "a" as an input. While
always @(*) begin
z = y;
y = a;
end
would report both "a" and "y" as inputs.
To fix this all nex_inputs now take a flag that when true (the default)
correctly removes any output from the input list. Both the above cases
will now return "a". If the flag is false outputs which are also inputs
will be included in the input list. This is what the @* elaboration code
uses to get the correct sensitivity list.
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <steve@icarus.com>
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
Cary R
Stephen Williams
Martin Whitaker
Larry Doolittle
Martin Whitaker
steve