156644d91e
Detect and complain about some constructor chain errors
...
This.new is not allowed.
super.new beyond the first statement is not allowed.
And while I'm at it, clean up the use of "@" and "#" in
the code as tokens for this and super.
2020-11-22 15:31:40 -08:00
1b3f0dd689
Add enumeration assignment compatibility check for continuous assignments.
2020-11-20 17:34:55 +00:00
a2ba8a16b1
Add support for inserting into a queue
2020-07-29 23:00:19 -07:00
6ecd43d947
Add/update queue compile time error messages
2020-07-25 16:33:30 -07:00
1a4345cce9
Add the ability to delete an element of a queue
2020-07-25 00:49:42 -07:00
8889886efd
Add assert to protect against potentially dereferencing null pointer.
...
Assert is apropriate, since it's not expected that the returned value is NULL in this case.
2020-07-11 03:54:29 +03:00
b36bca1f1b
Add support for return statements in void functions.
2020-07-10 23:34:11 +01:00
01ee6bd5b4
Fix how explicitly unconnected ports are handled in the presence of .*
...
See this PR: https://github.com/steveicarus/ivtest/pull/15
Which adds test implicit-port7
2020-05-18 22:49:05 +03:00
e19109e58f
Fix GitHub issue #316 - isolate modpath delays from multi-driven nets.
...
When module ports are collapsed, we can't tell which of the nexus drivers
are associated with a given module port and should be routed through an
associated modpath delay. Work round this by inserting a transparent
buffer or tran_vp if an output or inout port has a modpath delay. The
target code generator can elide this once it has handled the modpath
delays.
2020-05-07 22:51:38 +01:00
8da7a14800
Fix elaboration and evaluation of SV queue push arguments.
...
These are assignments to a queue element, so need to consider the
element base type when determining the expression width.
2020-05-01 15:30:44 +01:00
3f49dfcd97
Fix translation of module path connection type in vlog95 target.
...
The target API needed to be changed to pass the connection type
through to the target code generator.
2020-04-02 12:40:59 +01:00
a8f71d3c92
Additional cleanup of void function elaboration.
2019-11-09 20:15:31 +00:00
7feb26ff6b
Cleaner elaboration of void functions.
...
This fixed githun issue # 281.
2019-11-07 14:25:51 -08:00
de54a58991
Fix issue #265 - emit a sensible error message when an explicit cast is needed.
2019-10-06 17:54:44 +01:00
befc91340c
Parse and elaborate unique and priority case statements
...
The unique, unique0, and priority keywords can decorate case statements
to tell the run time (or synthesis) to do extra tests (or make extra
assumptions). These tests are not implemented in the vvp run time, but
now the decorations make it to the code generators.
2019-10-05 16:23:04 -07:00
862010ac19
SV does not require constant expression in variable initialisation.
2019-10-05 20:11:38 +01:00
9bb2147fb5
Merge branch 'package-imports-rework'
2019-10-01 23:04:23 +01:00
da36cee8f0
Detect errors elaborating delay expressions.
2019-10-01 09:29:13 -07:00
c5c264400e
Add support for package scope resolution for named events.
2019-10-01 09:07:54 +01:00
1e26a808ad
Fix error message for failed elaboration of event expression.
2019-10-01 09:07:30 +01:00
f69eccf903
Merge remote-tracking branch 'origin/master' into package-imports-rework
2019-10-01 09:06:15 +01:00
ba82ef463e
Fix some always_* issues
2019-09-29 16:59:59 -07:00
d3bced57cc
Correctly handle explicit and wildcard package imports.
...
Explicit imports should always conflict with local declarations using
the same name. Wildcard imports only conflict if they are referenced
before a local declaration with the same name.
This also unifies the detection of identifier conflicts.
2019-09-27 22:19:30 +01:00
55219773fd
Allow nested scopes to use their parent's imports.
2019-09-27 22:19:30 +01:00
02ee1c65d0
Support dynamic array initialisation in variable declarations.
2019-09-16 20:35:27 +01:00
a8318db21c
Fix assertion failure when top level module has array ports.
...
Reported by Kustaa Nyholm on iverilog-devel, 2017-10-17.
2019-08-03 18:52:49 +01:00
6309674a8d
Fix GitHub issue #231 - support packed array indexing in foreach statement.
2019-07-25 11:10:08 +01:00
0cb1ebddf1
Fix for GitHub issue #239 - segfault when library file has syntax errors.
...
If there are errors when parsing a file, it is not safe to elaborate any
modules that have been found in that file.
2019-07-24 10:22:55 +01:00
3f24557e90
Add some more always_ff synth checks
2018-09-23 22:32:22 -07:00
caf83b02c1
Enable variable declarations/initialisations in the compilation unit scope.
2018-02-18 14:09:03 +00:00
e7a9662b3d
A #0 is not allowed in a final block
2018-01-01 21:35:26 -08:00
2bbd077dc9
Add some synthesis checks for the always_comb/ff/latch blocks
2017-12-27 14:51:17 -08:00
f17992bcd0
Report the lines that have delay or event control in an always_comb/ff/latch process
2017-12-06 00:22:43 -08:00
cb0ffd734e
Check to see that always_comb/ff/latch do not have delays/events
2017-12-05 22:10:43 -08:00
575aa9b0fb
Fix spelling in always_comb
2017-12-03 20:17:42 -08:00
84d0df8a8a
Pass to the targets if an implicit T0 trigger event is needed.
2017-12-03 20:17:42 -08:00
585a0232cb
Add preliminary support for always_comb, always_ff and always_latch
2017-11-20 07:50:05 -08:00
fd807a7700
Rework handling of timescales in parser.
...
This implements and enforces the full set of rules for determining
timescales in SystemVerilog. The previous relaxation of the rules
that allowed timescales to be redefined within the compilation unit
scope has been removed. Time unit and precision redeclarations are
now recognised after a nested module declaration.
2017-11-05 17:50:05 +00:00
9382d22063
Factor out common code for warning about inconsistent timescales.
...
Also reword the warning for SystemVerilog, where `timescale is not
the only (or indeed preferred) way of specifying timescales.
2017-11-05 09:39:21 +00:00
988816c0b1
Support separate compilation units in SystemVerilog.
...
The compilation unit scope is now treated as a specialised form of
package (with an automatically generated name). All items declared
outside a design element are added to the current compilation unit
package. Apart from when searching for a symbol, once we get into
elaboration we can treat these just like any other package.
2017-10-31 20:38:59 +00:00
c967ed238c
Added option for ignoring errors about missing modules
2017-03-21 17:34:44 +02:00
002f118bb5
Fix for GitHub issue #130 part 1 - null dereference when assigning int to enum.
2016-11-25 21:53:35 +00:00
080dd0323d
Fix for GitHub issue #127 - coerce output ports to inout when necessary.
2016-09-17 19:20:48 +01:00
7bed181f68
Support timescales in design units that aren't inside a module.
...
SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.
2016-07-22 22:48:20 +01:00
e316cc708b
Fix assignment of outputs from class methods.
...
As for inputs, skip over the implicit 'this' parameter.
2016-07-21 19:06:21 +01:00
20104c92c8
Fix for GitHub issue #96 - support mixed constant/variable delays in vvp.
...
If all three rise/fall/decay delay values are constant, we can use
the vvp .delay statement variant that takes three literal numbers.
If not, we have to use the variant that takes three net inputs. If
some of the delay values are constant, we need to create constant
drivers for those delay inputs.
2016-04-02 19:55:56 +01:00
72bb63cf42
Variable initialization blocks should be unamed.
...
Also add file/line info to initial process.
2016-03-19 14:21:10 +00:00
54feb89bf5
For SystemVerilog, run variable initialization before main simulation starts.
2016-03-19 13:46:09 +00:00
635adfc01e
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 13:04:38 +00:00
c4b3f256af
Don't mislabel signals as ports when casting port connections.
...
The original signal should retain the port type. Moving it to the cast
signal was confusing the vlog95 and stub targets.
2016-03-12 23:17:54 +00:00
Stephen Williams
Martin Whitaker
Cary R
Purdea Andrei
Purdea Andrei
Mikael Tuomisalo