James Cherry
|
16f3f94b5b
|
Klockwork warnings
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2022-01-15 12:51:05 -07:00 |
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James Cherry
|
2bc6e8f68c
|
update copyright
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2022-01-04 10:17:08 -07:00 |
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James Cherry
|
65774f4bdd
|
read_sdc gzip files
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2021-11-14 17:53:25 -07:00 |
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James Cherry
|
46a835a581
|
write_verilog assigns for nets with multiple output ports
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2021-10-08 10:51:05 -07:00 |
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James Cherry
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85f437bc59
|
verilog black box ports unknown/loads
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2021-09-17 08:35:45 -07:00 |
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James Cherry
|
8c23d8ef83
|
read_verilog/link_design support redirection
|
2021-07-09 11:25:05 -07:00 |
|
James Cherry
|
b9116bd56d
|
read_verilog no warn on pg_pin connections
|
2021-07-07 16:57:34 -07:00 |
|
James Cherry
|
2e8f0035dc
|
update copyright
|
2021-06-25 10:25:49 -07:00 |
|
James Cherry
|
61df23741d
|
write_verilog w/o -include_pwr_gnd exclude top pwr/gnd port and dcl
|
2021-02-19 09:06:27 -08:00 |
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James Cherry
|
6359bd6fc5
|
leaks
|
2021-02-07 17:22:59 +00:00 |
|
James Cherry
|
d00937f981
|
write_verilog wire stmts
|
2021-01-19 12:40:49 -07:00 |
|
James Cherry
|
c13383fbb3
|
issue#31 verilog concat assign
|
2021-01-19 11:17:13 -07:00 |
|
James Cherry
|
54dbbf625e
|
mv debug_on into Debug
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2021-01-04 20:47:37 -08:00 |
|
James Cherry
|
9b1dc880f5
|
rm Debug::print
|
2020-12-29 10:33:22 -08:00 |
|
James Cherry
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ee86a30338
|
error/warn
|
2020-12-25 14:00:11 -08:00 |
|
James Cherry
|
1a99dd0aff
|
cmd filename args with spaces
|
2020-12-23 08:02:56 -08:00 |
|
James Cherry
|
78d29c8f90
|
error/warn IDs
|
2020-12-13 18:21:35 -07:00 |
|
James Cherry
|
b4851a6c7d
|
flex disable register decls
|
2020-11-11 08:32:25 -07:00 |
|
James Cherry
|
c9296a0d1f
|
disable flex register warnings
|
2020-11-09 21:11:29 -07:00 |
|
James Cherry
|
01a1ab6707
|
write_verilog -remove_cells
|
2020-10-20 12:16:17 -07:00 |
|
James Cherry
|
fc279f0b34
|
write_verilog -include_pwr_gnd
|
2020-10-19 20:55:54 -07:00 |
|
James Cherry
|
7d31cfac8f
|
flex disable register declarations
|
2020-09-17 05:50:12 -07:00 |
|
James Cherry
|
1c8f1ec9fc
|
VerilogWriter using instead of include for LibertyCell
|
2020-07-18 09:12:38 -07:00 |
|
James Cherry
|
a5722ae63c
|
write_verilog remove_cells use std::vector
|
2020-07-15 11:56:11 -07:00 |
|
James Cherry
|
4fa9e46235
|
write_verilog -remove_cells
|
2020-07-15 07:56:34 -07:00 |
|
James Cherry
|
e7ed3170f3
|
write_verilog power/ground port dcls
|
2020-07-03 16:56:15 -07:00 |
|
James Cherry
|
a862935b38
|
verilog port input tri -> input
|
2020-05-04 17:13:48 -07:00 |
|
James Cherry
|
ec856896c7
|
verilog read/write to public includes
|
2020-04-05 16:56:38 -07:00 |
|
James Cherry
|
ee326f165c
|
public headers in include/sta
|
2020-04-05 14:53:44 -07:00 |
|
James Cherry
|
804953e317
|
mv public headers to include/sta
|
2020-04-05 11:35:51 -07:00 |
|
James Cherry
|
4a017e86eb
|
update copyright
|
2020-03-06 18:50:37 -08:00 |
|
James Cherry
|
88c9cd3c39
|
comment
|
2020-02-15 17:13:34 -07:00 |
|
James Cherry
|
3d6d6e9580
|
use #pragma once
|
2020-02-15 17:13:16 -07:00 |
|
James Cherry
|
7fdeb0d3b7
|
use range iter
|
2020-02-01 18:13:41 -07:00 |
|
James Cherry
|
26c76cd075
|
verilog reader make instances with liberty cell
|
2020-02-01 10:55:27 -07:00 |
|
James Cherry
|
1068813b59
|
UseSWIG cmake support for swig
|
2020-01-25 10:38:03 -07:00 |
|
James Cherry
|
d22eaea30c
|
flush Makefile.am
|
2020-01-04 19:00:51 -08:00 |
|
James Cherry
|
74e287a7eb
|
write_verilog escaped bus port name "input [7:0] \in[0] ;"
|
2019-07-03 21:18:38 -07:00 |
|
James Cherry
|
7af69066df
|
VerilogWriter use liberty bus port order
|
2019-07-02 16:33:31 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
|
2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
d108a15c56
|
write_verilog fails for missing pins
|
2019-06-27 18:04:57 -07:00 |
|
James Cherry
|
5d7ad0a1ef
|
write_verilog use concat for instance bus ports
|
2019-06-27 16:06:46 -07:00 |
|
James Cherry
|
344394de29
|
link_design use verilog library to lookup top
|
2019-06-26 16:01:58 -07:00 |
|
James Cherry
|
1a84830895
|
sta::worst_slack args, sta to verilog name args
|
2019-06-18 15:52:12 -07:00 |
|
James Cherry
|
eea6ab1a29
|
write_verilog -sorted -> -sort
|
2019-06-17 12:33:37 -07:00 |
|
James Cherry
|
49b2c3cea7
|
rm redundant StaState args
|
2019-06-17 08:32:28 -07:00 |
|
James Cherry
|
3f7e207491
|
write_verilog
|
2019-06-16 21:08:00 -07:00 |
|
James Cherry
|
96fcf1d8b2
|
ConcreteCell/Port pointers to corresponding liberty
|
2019-06-15 22:20:54 -07:00 |
|
James Cherry
|
a988588dac
|
sync
|
2019-05-19 17:06:06 -06:00 |
|
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
92f4968feb
|
write_path_spice bug fixes
|
2019-01-20 09:44:24 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
3d8d088b89
|
sync
|
2019-01-05 16:09:27 -08:00 |
|
James Cherry
|
9e5aac37f4
|
cmake, write_path_spice
|
2019-01-03 16:14:15 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
|
James Cherry
|
e9bde796ec
|
2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
|
2018-11-09 10:04:16 -08:00 |
|
James Cherry
|
2af22d9331
|
2018/10/23 read_verilog mod inst with no ports seg fault
|
2018-10-23 16:24:22 -07:00 |
|
James Cherry
|
e68203dcf4
|
^/v for arc display
|
2018-10-02 16:20:18 -07:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |