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write_verilog power/ground port dcls

This commit is contained in:
James Cherry 2020-07-03 16:56:15 -07:00
parent 220f280c02
commit e7ed3170f3
1 changed files with 11 additions and 3 deletions
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14
verilog/VerilogWriter.cc
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@ -165,12 +165,20 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
return "input";
else if (dir == PortDirection::output())
return "output";
else if (dir == PortDirection::bidirect())
return "inout";
else if (dir == PortDirection::tristate())
return "output";
else
else if (dir == PortDirection::bidirect())
return "inout";
else if (dir == PortDirection::power())
return "input";
else if (dir == PortDirection::ground())
return "input";
else if (dir == PortDirection::internal())
return nullptr;
else {
internalError("unknown port direction");
return nullptr;
}
}
void