rm Debug::print
This commit is contained in:
parent
72aaf962c6
commit
9b1dc880f5
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@ -486,16 +486,16 @@ ArnoldiReduce::makeRcmodelFromTs()
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for (k=0;k<ts_ordN;k++) {
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p = ts_pordV[k];
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debugPrint3(debug_, "arnoldi", 1, "T%d,P%ld c=%s",
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p->ts,p-p0,
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p->ts,
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p-p0,
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units_->capacitanceUnit()->asString(p->c));
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if (p->is_term)
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debug_->print(" term%d", p->tindex);
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debugPrint1(debug_, "arnoldi", 1, " term %d", p->tindex);
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if (p->in_edge)
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debug_->print(" from T%d,P%ld r=%s",
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p->in_edge->from->ts,
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p->in_edge->from-p0,
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units_->resistanceUnit()->asString(p->r));
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debug_->print("\n");
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debugPrint3(debug_, "arnoldi", 1, " from T%d,P%ld r=%s",
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p->in_edge->from->ts,
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p->in_edge->from-p0,
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units_->resistanceUnit()->asString(p->r));
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}
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for (i=0;i<nterms;i++)
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debugPrint2(debug_, "arnoldi", 1, "outV[%d] = T%d", i, outV[i]);
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@ -587,23 +587,25 @@ ArnoldiReduce::makeRcmodelFromTs()
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}
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if (debug_->check("arnoldi", 1)) {
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debugPrint1(debug_, "arnoldi", 1,
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"tridiagonal reduced matrix, drvr pin %s",
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network_->pathName(drvr_pin_));
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debugPrint2(debug_, "arnoldi", 1, "order %d n %d",order,n);
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report_->reportLine("tridiagonal reduced matrix, drvr pin %s",
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network_->pathName(drvr_pin_));
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report_->reportLine("order %d n %d",order,n);
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for (h=0;h<order;h++) {
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debug_->print("d[%d] %s",
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h,
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units_->timeUnit()->asString(d[h]));
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if (h<order-1)
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debug_->print(" e[%d] %s",
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h,
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units_->timeUnit()->asString(e[h]));
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debug_->print("\n");
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debug_->print("U[%d]",h);
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report_->reportLine(" d[%d] %s e[%d] %s",
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h,
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units_->timeUnit()->asString(d[h]),
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h,
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units_->timeUnit()->asString(e[h]));
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else
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report_->reportLine(" d[%d] %s",
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h,
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units_->timeUnit()->asString(d[h]));
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string line = stdstrPrint("U[%d]",h);
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for (i=0;i<nterms;i++)
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debug_->print(" %6.2e",U[h][i]);
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debug_->print("\n");
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line += stdstrPrint(" %6.2e",U[h][i]);
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report_->reportLine(line);
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}
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}
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}
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@ -462,28 +462,29 @@ void
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DmpAlg::showX()
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{
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for (int i = 0; i < nr_order_; i++)
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debug_->print("%4s %12.3e\n", dmp_param_index_strings[i], x_[i]);
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report_->reportLine("%4s %12.3e", dmp_param_index_strings[i], x_[i]);
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}
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void
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DmpAlg::showFvec()
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{
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for (int i = 0; i < nr_order_; i++)
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debug_->print("%4s %12.3e\n", dmp_func_index_strings[i], fvec_[i]);
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report_->reportLine("%4s %12.3e", dmp_func_index_strings[i], fvec_[i]);
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}
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void
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DmpAlg::showJacobian()
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{
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debug_->print(" ");
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string line = " ";
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for (int j = 0; j < nr_order_; j++)
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debug_->print("%12s", dmp_param_index_strings[j]);
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debug_->print("\n");
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line += stdstrPrint("%12s", dmp_param_index_strings[j]);
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report_->reportLine(line);
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line.clear();
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for (int i = 0; i < nr_order_; i++) {
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debug_->print("%4s ", dmp_func_index_strings[i]);
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line += stdstrPrint("%4s ", dmp_func_index_strings[i]);
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for (int j = 0; j < nr_order_; j++)
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debug_->print("%12.3e ", fjac_[i][j]);
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debug_->print("\n");
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line += stdstrPrint("%12.3e ", fjac_[i][j]);
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report_->reportLine(line);
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}
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}
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@ -545,12 +546,10 @@ DmpAlg::dVoDt(double t)
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void
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DmpAlg::showVo()
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{
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debug_->print(" t vo(t)\n");
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report_->reportLine(" t vo(t)");
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double ub = voCrossingUpperBound();
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for (double t = t0_; t < t0_ + ub; t += dt_ / 10.0)
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debug_->print(" %g %g\n", t, vo(t));
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// debug_->print(" %.3g %.3g", t-t0_, vo(t)*3);
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// debug_->print("\n");
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report_->reportLine(" %g %g", t, vo(t));
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}
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void
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@ -658,10 +657,10 @@ DmpAlg::dVlDt(double t)
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void
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DmpAlg::showVl()
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{
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debug_->print(" t vl(t)\n");
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report_->reportLine(" t vl(t)");
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double ub = vlCrossingUpperBound();
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for (double t = t0_; t < t0_ + ub * 2.0; t += ub / 10.0)
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debug_->print(" %g %g\n", t, vl(t));
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report_->reportLine(" %g %g", t, vl(t));
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}
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void
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@ -669,12 +668,12 @@ DmpAlg::fail(const char *reason)
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{
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// Allow only failures to be reported with a unique debug flag.
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if (debug_->check("dmp_ceff", 1) || debug_->check("dmp_ceff_fail", 1))
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debug_->print("delay_calc: DMP failed - %s c2=%s rpi=%s c1=%s rd=%s\n",
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reason,
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units_->capacitanceUnit()->asString(c2_),
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units_->resistanceUnit()->asString(rpi_),
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units_->capacitanceUnit()->asString(c1_),
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units_->resistanceUnit()->asString(rd_));
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report_->reportLine("delay_calc: DMP failed - %s c2=%s rpi=%s c1=%s rd=%s",
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reason,
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units_->capacitanceUnit()->asString(c2_),
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units_->resistanceUnit()->asString(rpi_),
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units_->capacitanceUnit()->asString(c1_),
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units_->resistanceUnit()->asString(rd_));
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}
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////////////////////////////////////////////////////////////////
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@ -1001,7 +1000,7 @@ DmpPi::evalDmpEqns()
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showX();
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showFvec();
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showJacobian();
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debug_->print(".................\n");
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report_->reportLine(".................");
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}
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}
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@ -1112,7 +1111,7 @@ DmpOnePole::evalDmpEqns()
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if (debug_->check("dmp_ceff", 4)) {
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showJacobian();
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debug_->print(".................\n");
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report_->reportLine(".................");
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}
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}
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@ -402,7 +402,7 @@ void
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GraphDelayCalc1::findDelays(Level level)
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{
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if (arc_delay_calc_) {
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Stats stats(debug_);
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Stats stats(debug_, report_);
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int dcalc_count = 0;
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debugPrint1(debug_, "delay_calc", 1, "find delays to level %d", level);
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if (!delays_seeded_) {
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@ -67,7 +67,7 @@ Graph::~Graph()
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void
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Graph::makeGraph()
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{
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Stats stats(debug_);
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Stats stats(debug_, report_);
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makeVerticesAndEdges();
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makeWireEdges();
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stats.report("Make graph");
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@ -45,9 +45,6 @@ public:
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void setLevel(const char *what,
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int level);
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int statsLevel() const { return stats_level_; }
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void print(const char *fmt,
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...) const
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__attribute__((format (printf, 2, 3)));
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void reportLine(const char *what,
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const char *fmt,
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...) const
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@ -22,12 +22,14 @@
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namespace sta {
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class Debug;
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class Report;
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// Show run time and memory statistics if the "stats" debug flag is on.
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class Stats
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{
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public:
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explicit Stats(Debug *debug);
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explicit Stats(Debug *debug,
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Report *report);
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void report(const char *step);
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private:
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@ -38,6 +40,7 @@ private:
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double system_begin_;
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size_t memory_begin_;
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Debug *debug_;
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Report *report_;
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};
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} // namespace
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@ -34,7 +34,7 @@ annotateGraphDisabledWireEdge(Pin *from_pin,
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void
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Sdc::annotateGraph()
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{
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Stats stats(debug_);
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Stats stats(debug_, report_);
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// All output pins are considered constrained because
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// they may be downstream from a set_min/max_delay -from that
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// does not have a set_output_delay.
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@ -194,7 +194,7 @@ void
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Genclks::ensureInsertionDelays()
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{
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if (!found_insertion_delays_) {
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Stats stats(debug_);
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Stats stats(debug_, report_);
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debugPrint0(debug_, "genclk", 1, "find generated clk insertion delays");
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ClockSeq gclks;
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@ -114,7 +114,7 @@ Levelize::ensureLevelized()
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void
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Levelize::levelize()
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{
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Stats stats(debug_);
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Stats stats(debug_, report_);
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debugPrint0(debug_, "levelize", 1, "levelize");
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max_level_ = 0;
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clearLoopEdges();
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@ -176,10 +176,10 @@ PathEnum::findNext()
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Vertex *vertex = path_end->vertex(this);
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if (debug_->check("path_enum", 2)) {
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Path *path = path_end->path();
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debug_->print("path_enum: next path %s delay %s slack %s\n",
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path->name(this),
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delayAsString(path_end->dataArrivalTime(this), this),
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delayAsString(path_end->slack(this), this));
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report_->reportLine("path_enum: next path %s delay %s slack %s",
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path->name(this),
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delayAsString(path_end->dataArrivalTime(this), this),
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delayAsString(path_end->slack(this), this));
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reportDiversionPath(div);
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}
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@ -211,10 +211,10 @@ PathEnum::reportDiversionPath(Diversion *div)
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path->prevPath(this, p);
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Path *after_div = div->divPath();
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while (!p.isNull()) {
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debug_->print("path_enum: %s %s%s\n",
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p.name(this),
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delayAsString(p.arrival(this), this),
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Path::equal(&p, after_div, this) ? " <-diversion" : "");
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report_->reportLine("path_enum: %s %s%s",
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p.name(this),
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delayAsString(p.arrival(this), this),
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Path::equal(&p, after_div, this) ? " <-diversion" : "");
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if (network_->isLatchData(p.pin(this)))
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break;
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p.prevPath(this, p);
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@ -387,6 +387,7 @@ PathEnumFaninVisitor::reportDiversion(TimingArc *div_arc,
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{
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Debug *debug = sta_->debug();
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if (debug->check("path_enum", 3)) {
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Report *report = sta_->report();
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Path *path = path_end_->path();
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const PathAnalysisPt *path_ap = path->pathAnalysisPt(sta_);
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Arrival path_delay = path_enum_->cmp_slack_
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@ -397,16 +398,16 @@ PathEnumFaninVisitor::reportDiversion(TimingArc *div_arc,
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div_arc, path_ap);
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PathRef div_prev;
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before_div_.prevPath(sta_, div_prev);
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debug->print("path_enum: diversion %s %s %s -> %s\n",
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path->name(sta_),
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path_enum_->cmp_slack_ ? "slack" : "delay",
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delayAsString(path_delay, sta_),
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delayAsString(div_delay, sta_));
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debug->print("path_enum: from %s -> %s\n",
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div_prev.name(sta_),
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before_div_.name(sta_));
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debug->print("path_enum: to %s ->\n",
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after_div->name(sta_));
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report->reportLine("path_enum: diversion %s %s %s -> %s",
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path->name(sta_),
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path_enum_->cmp_slack_ ? "slack" : "delay",
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delayAsString(path_delay, sta_),
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delayAsString(div_delay, sta_));
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report->reportLine("path_enum: from %s -> %s",
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div_prev.name(sta_),
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before_div_.name(sta_));
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report->reportLine("path_enum: to %s ->e",
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after_div->name(sta_));
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}
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}
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@ -490,7 +490,7 @@ PathGroups::makePathEnds(ExceptionTo *to,
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const MinMaxAll *min_max,
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bool sort_by_slack)
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{
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Stats stats(this->debug());
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Stats stats(debug_, report_);
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makeGroupPathEnds(to, group_count_, endpoint_count_, unique_pins_,
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corner, min_max);
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@ -783,7 +783,7 @@ Search::findClkArrivals()
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{
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if (!clk_arrivals_valid_) {
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genclks_->ensureInsertionDelays();
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Stats stats(debug_);
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Stats stats(debug_, report_);
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debugPrint0(debug_, "search", 1, "find clk arrivals");
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arrival_iter_->clear();
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seedClkVertexArrivals();
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@ -960,7 +960,7 @@ Search::findArrivals(Level level,
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{
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debugPrint1(debug_, "search", 1, "find arrivals to level %d", level);
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findArrivals1();
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Stats stats(debug_);
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Stats stats(debug_, report_);
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int arrival_count = arrival_iter_->visitParallel(level, arrival_visitor);
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stats.report("Find arrivals");
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if (arrival_iter_->empty()
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@ -3070,7 +3070,7 @@ Search::findRequireds()
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void
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Search::findRequireds(Level level)
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{
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Stats stats(debug_);
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Stats stats(debug_, report_);
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debugPrint1(debug_, "search", 1, "find requireds to level %d", level);
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RequiredVisitor req_visitor(this);
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if (!requireds_seeded_)
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@ -3118,7 +3118,8 @@ Search::endpoints()
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else {
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if (debug_->check("endpoint", 2)
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&& endpoints_->hasKey(vertex))
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debug_->print("endpoint: remove %s\n", vertex->name(sdc_network_));
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report_->reportLine("endpoint: remove %s",
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vertex->name(sdc_network_));
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endpoints_->erase(vertex);
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}
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}
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@ -539,7 +539,7 @@ void
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Sim::ensureConstantsPropagated()
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{
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if (!valid_) {
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Stats stats(debug_);
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Stats stats(debug_, report_);
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ensureConstantFuncPins();
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instances_to_annotate_.clear();
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if (incremental_) {
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@ -642,7 +642,7 @@ Sta::readLiberty(const char *filename,
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const MinMaxAll *min_max,
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bool infer_latches)
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{
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Stats stats(debug_);
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Stats stats(debug_, report_);
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LibertyLibrary *library = readLibertyFile(filename, corner, min_max,
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infer_latches, network_);
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if (library
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@ -726,7 +726,7 @@ bool
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Sta::linkDesign(const char *top_cell_name)
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{
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clear();
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Stats stats(debug_);
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Stats stats(debug_, report_);
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bool status = network_->linkNetwork(top_cell_name,
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link_make_black_boxes_,
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report_);
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@ -102,16 +102,6 @@ Debug::setLevel(const char *what,
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}
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}
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void
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Debug::print(const char *fmt,
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...) const
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{
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va_list args;
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va_start(args, fmt);
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report_->vprint(fmt, args);
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va_end(args);
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}
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void
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Debug::reportLine(const char *what,
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const char *fmt,
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@ -18,12 +18,15 @@
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#include "Machine.hh"
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#include "StringUtil.hh"
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#include "Report.hh"
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#include "Debug.hh"
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namespace sta {
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Stats::Stats(Debug *debug) :
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debug_(debug)
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Stats::Stats(Debug *debug,
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Report *report) :
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debug_(debug),
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report_(report)
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{
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if (debug->statsLevel() > 0) {
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elapsed_begin_ = elapsedRunTime();
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@ -42,11 +45,11 @@ Stats::report(const char *step)
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double memory_begin = static_cast<double>(memory_begin_);
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double memory_end = static_cast<double>(memoryUsage());
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double memory_delta = memory_end - memory_begin;
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debug_->print("stats: %5.1f/%5.1fe %5.1f/%5.1fu %5.1f/%5.1fMB %s\n",
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elapsed_end - elapsed_begin_, elapsed_end,
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||||
user_end - user_begin_, user_end,
|
||||
memory_delta * 1e-6, memory_end * 1e-6,
|
||||
step);
|
||||
report_->reportLine("stats: %5.1f/%5.1fe %5.1f/%5.1fu %5.1f/%5.1fMB %s",
|
||||
elapsed_end - elapsed_begin_, elapsed_end,
|
||||
user_end - user_begin_, user_end,
|
||||
memory_delta * 1e-6, memory_end * 1e-6,
|
||||
step);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -183,7 +183,7 @@ VerilogReader::read(const char *filename)
|
|||
// Use zlib to uncompress gzip'd files automagically.
|
||||
stream_ = gzopen(filename, "rb");
|
||||
if (stream_) {
|
||||
Stats stats(debug_);
|
||||
Stats stats(debug_, report_);
|
||||
init(filename);
|
||||
bool success = (::VerilogParse_parse() == 0);
|
||||
gzclose(stream_);
|
||||
|
|
@ -682,20 +682,20 @@ VerilogReader::incrLine()
|
|||
}
|
||||
|
||||
#define printClassMemory(name, class_name, count) \
|
||||
debug_->print(" %-20s %9d * %3d = %6.1fMb\n", \
|
||||
name, \
|
||||
count, \
|
||||
static_cast<int>(sizeof(class_name)), \
|
||||
(count * sizeof(class_name) * 1e-6))
|
||||
report_->reportLine(" %-20s %9d * %3d = %6.1fMb\n", \
|
||||
name, \
|
||||
count, \
|
||||
static_cast<int>(sizeof(class_name)), \
|
||||
(count * sizeof(class_name) * 1e-6))
|
||||
|
||||
#define printStringMemory(name, count) \
|
||||
debug_->print(" %-20s %6.1fMb\n", name, count * 1e-6)
|
||||
report_->reportLine(" %-20s %6.1fMb", name, count * 1e-6)
|
||||
|
||||
void
|
||||
VerilogReader::reportStmtCounts()
|
||||
{
|
||||
if (debugCheck(debug_, "verilog", 1)) {
|
||||
debug_->print("Verilog stats\n");
|
||||
report_->reportLine("Verilog stats");
|
||||
printClassMemory("modules", VerilogModule, module_count_);
|
||||
printClassMemory("module insts", VerilogModuleInst, inst_mod_count_);
|
||||
printClassMemory("liberty insts", VerilogLibertyInst, inst_lib_count_);
|
||||
|
|
|
|||
Loading…
Reference in New Issue