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write_verilog fails for missing pins

This commit is contained in:
James Cherry 2019-06-27 18:04:57 -07:00
parent 5d7ad0a1ef
commit d108a15c56
1 changed files with 20 additions and 16 deletions
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36
verilog/VerilogWriter.cc
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@ -205,12 +205,14 @@ VerilogWriter::writeChild(Instance *child)
while (member_iter->hasNext()) {
Port *member = member_iter->next();
Pin *pin = network_->findPin(child, member);
Net *net = network_->net(pin);
const char *net_name;
if (net)
net_name = network_->name(net);
else
// I can't see the verilog syntax to "skip" a bit in the concatentation.
const char *net_name = nullptr;
if (pin) {
Net *net = network_->net(pin);
if (net)
net_name = network_->name(net);
}
if (net_name == nullptr)
// There is no verilog syntax to "skip" a bit in the concatentation.
net_name = stringPrintTmp("_NC%d", unconnected_net_index_++);
const char *net_vname = netVerilogName(net_name, network_->pathEscape());
if (!first_member)
@ -223,16 +225,18 @@ VerilogWriter::writeChild(Instance *child)
}
else {
Pin *pin = network_->findPin(child, port);
Net *net = network_->net(pin);
if (net) {
const char *net_name = network_->name(net);
const char *net_vname = netVerilogName(net_name, network_->pathEscape());
if (!first_port)
fprintf(stream_, ",\n ");
fprintf(stream_, ".%s(%s)",
port_name,
net_vname);
first_port = false;
if (pin) {
Net *net = network_->net(pin);
if (net) {
const char *net_name = network_->name(net);
const char *net_vname = netVerilogName(net_name, network_->pathEscape());
if (!first_port)
fprintf(stream_, ",\n ");
fprintf(stream_, ".%s(%s)",
port_name,
net_vname);
first_port = false;
}
}
}
}