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verilog port input tri -> input

This commit is contained in:
James Cherry 2020-05-04 17:13:48 -07:00
parent 823f754806
commit a862935b38
1 changed files with 5 additions and 5 deletions
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10
verilog/VerilogReader.cc
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@ -815,13 +815,13 @@ VerilogModule::parseDcl(VerilogDcl *dcl,
// wire dcl can be used as modifier for input/inout dcls.
// Ignore the wire dcl.
dcl_map_[net_name] = dcl;
else if (dcl->direction()->isTristate()
&& (existing_dir->isOutput()
|| existing_dir->isInput()
|| existing_dir->isBidirect()))
else if (dcl->direction()->isTristate()) {
if (existing_dir->isOutput())
// tri dcl can be used as modifier for input/output/inout dcls.
// Keep the tristate dcl because it is more specific.
// Keep the tristate dcl for outputs because it is more specific
// but ignore it for inputs and bidirs.
dcl_map_[net_name] = dcl;
}
else if (dcl->direction()->isPowerGround()
&& (existing_dir->isOutput()
|| existing_dir->isInput()