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issue#31 verilog concat assign

This commit is contained in:
James Cherry 2021-01-19 11:17:13 -07:00
parent d418537bcc
commit c13383fbb3
1 changed files with 7 additions and 2 deletions
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9
verilog/VerilogParse.yy
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@ -64,7 +64,7 @@ int VerilogLex_lex();
%type <assign> net_assignment
%type <dcl_arg> dcl_arg
%type <dcl_arg_seq> dcl_args
%type <net> port net_scalar net_bit_select net_part_select
%type <net> port net_scalar net_bit_select net_part_select net_assign_lhs
%type <net> net_constant net_expr port_ref port_expr named_pin_net_expr
%type <net> inst_named_pin net_named net_expr_concat
%type <nets> port_list port_refs inst_ordered_pins
@ -334,10 +334,15 @@ net_assignments:
;
net_assignment:
net_named { $<ival>$ = sta::verilog_reader->line(); } '=' net_expr
net_assign_lhs { $<ival>$ = sta::verilog_reader->line(); } '=' net_expr
{ $$ = sta::verilog_reader->makeAssign($1, $4, $<ival>2); }
;
net_assign_lhs:
net_named
| net_expr_concat
;
instance:
ID { $<ival>$ = sta::verilog_reader->line(); } ID '(' inst_pins ')' ';'
{ $$ = sta::verilog_reader->makeModuleInst($1, $3, $5, $<ival>2); }