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write_verilog assigns for nets with multiple output ports 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2021-10-08 10:51:05 -07:00
parent 83f58d320f
commit 46a835a581
1 changed files with 27 additions and 0 deletions
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27
verilog/VerilogWriter.cc
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@ -59,6 +59,7 @@ protected:
void writeInstBusPinBit(Instance *inst,
Port *port,
bool &first_member);
void writeAssigns(Instance *inst);
const char *filename_;
bool sort_;
@ -123,6 +124,7 @@ VerilogWriter::writeModule(Instance *inst)
writeWireDcls(inst);
fprintf(stream_, "\n");
writeChildren(inst);
writeAssigns(inst);
fprintf(stream_, "endmodule\n");
written_cells_.insert(cell);
@ -375,4 +377,29 @@ VerilogWriter::writeInstBusPinBit(Instance *inst,
first_member = false;
}
// Verilog "ports" are not distinct from nets.
// Use an assign statement to alias the net when it is connected to
// multiple output ports.
void
VerilogWriter::writeAssigns(Instance *inst)
{
InstancePinIterator *pin_iter = network_->pinIterator(inst);
while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next();
Term *term = network_->term(pin);
Net *net = network_->net(term);
Port *port = network_->port(pin);
if (network_->direction(port)->isAnyOutput()
&& !stringEqual(network_->name(port), network_->name(net))) {
// Port name is different from net name.
fprintf(stream_, " assign %s = %s;\n",
netVerilogName(network_->name(port),
network_->pathEscape()),
netVerilogName(network_->name(net),
network_->pathEscape()));
}
}
delete pin_iter;
}
} // namespace