ConcreteCell/Port pointers to corresponding liberty

liberty/Liberty.cc

@@ -871,6 +871,7 @@ LibertyCell::LibertyCell(LibertyLibrary *library,
   higher_drive_(nullptr),
   lower_drive_(nullptr)
 {
+  liberty_cell_ = this;
 }
 
 LibertyCell::~LibertyCell()
@@ -1874,6 +1875,7 @@ LibertyPort::LibertyPort(LibertyCell *cell,
   is_pll_feedback_pin_(false),
   is_disabled_constraint_(false)
 {
+  liberty_port_ = this;
   min_pulse_width_[TransRiseFall::riseIndex()] = 0.0;
   min_pulse_width_[TransRiseFall::fallIndex()] = 0.0;
 }

network/ConcreteLibrary.cc

@@ -112,6 +112,7 @@ ConcreteCell::ConcreteCell(ConcreteLibrary *library,
   library_(library),
   name_(stringCopy(name)),
   filename_(stringCopy(filename)),
+  liberty_cell_(nullptr),
   port_bit_count_(0),
   is_leaf_(is_leaf)
 {
@@ -134,6 +135,12 @@ ConcreteCell::setName(const char *name)
   name_ = name_cpy;
 }
 
+void
+ConcreteCell::setLibertyCell(LibertyCell *cell)
+{
+  liberty_cell_ = cell;
+}
+
 ConcretePort *
 ConcreteCell::makePort(const char *name)
 {
@@ -422,6 +429,7 @@ ConcretePort::ConcretePort(ConcreteCell *cell,
   name_(stringCopy(name)),
   cell_(cell),
   direction_(PortDirection::unknown()),
+  liberty_port_(nullptr),
   pin_index_(-1),
   is_bundle_(is_bundle),
   is_bus_(is_bus),
@@ -447,6 +455,12 @@ ConcretePort::cell() const
   return reinterpret_cast<Cell*>(cell_);
 }
 
+void
+ConcretePort::setLibertyPort(LibertyPort *port)
+{
+  liberty_port_ = port;
+}
+
 const char *
 ConcretePort::busName() const
 {

network/ConcreteLibrary.hh

@@ -34,6 +34,8 @@ class ConcreteCell;
 class ConcretePort;
 class ConcreteCellPortBitIterator;
 class PatternMatch;
+class LibertyCell;
+class LibertyPort;
 
 typedef Map<const char*, ConcreteCell*, CharPtrLess> ConcreteCellMap;
 typedef Vector<ConcretePort*> ConcretePortSeq;
@@ -89,6 +91,8 @@ public:
   virtual ConcreteLibrary *library() const { return library_; }
   virtual const char *name() const { return name_; }
   virtual const char *filename() const { return filename_; }
+  LibertyCell *libertyCell() { return liberty_cell_; }
+  void setLibertyCell(LibertyCell *cell);
   virtual int portBitCount() const { return port_bit_count_; }
   virtual ConcretePort *findPort(const char *name) const;
   virtual void findPortsMatching(const PatternMatch *pattern,
@@ -139,6 +143,7 @@ protected:
   const char *name_;
   // Filename is optional.
   const char *filename_;
+  LibertyCell *liberty_cell_;
   // Non-bus and bus ports (but no expanded bus bit ports).
   ConcretePortSeq ports_;
   ConcretePortMap port_map_;
@@ -162,6 +167,8 @@ public:
   virtual Cell *cell() const;
   virtual ConcreteLibrary *library() const { return cell_->library(); }
   virtual PortDirection *direction() const { return direction_; }
+  LibertyPort *libertyPort() { return liberty_port_; }
+  void setLibertyPort(LibertyPort *port);
   virtual void setDirection(PortDirection *dir);
   // Bundles are groups of related ports that do not use
   // bus notation.
@@ -209,6 +216,7 @@ protected:
   const char *name_;
   ConcreteCell *cell_;
   PortDirection *direction_;
+  LibertyPort *liberty_port_;
   int pin_index_;
   bool is_bundle_;
   bool is_bus_;

network/ConcreteNetwork.cc

@@ -550,7 +550,7 @@ LibertyCell *
 ConcreteNetwork::libertyCell(Cell *cell) const
 {
   ConcreteCell *ccell = reinterpret_cast<ConcreteCell*>(cell);
-  return dynamic_cast<LibertyCell*>(ccell);
+  return ccell->libertyCell();
 }
 
 Cell *
@@ -743,7 +743,7 @@ LibertyPort *
 ConcreteNetwork::libertyPort(Port *port) const
 {
   ConcretePort *cport = reinterpret_cast<ConcretePort*>(port);
-  return dynamic_cast<LibertyPort*>(cport);
+  return cport->libertyPort();
 }
 
 PortDirection *

verilog/VerilogReader.cc

@@ -539,8 +539,9 @@ VerilogReader::makeModuleInst(const char *module_name,
 			      const int line)
 {
   Cell *cell = network_->findAnyCell(module_name);
-  LibertyCell *liberty_cell = network_->libertyCell(cell);
-  VerilogInst *inst;
+  LibertyCell *liberty_cell = nullptr;
+  if (cell)
+    liberty_cell = network_->libertyCell(cell);
   // Instances of liberty with scalar ports are special cased
   // to reduce the memory footprint of the verilog parser.
   if (liberty_cell
@@ -573,7 +574,8 @@ VerilogReader::makeModuleInst(const char *module_name,
       delete vpin;
       net_port_ref_scalar_net_count_--;
     }
-    inst = new VerilogLibertyInst(liberty_cell, inst_name, net_names, line);
+    VerilogInst *inst = new VerilogLibertyInst(liberty_cell, inst_name,
+					       net_names, line);
     stringDelete(module_name);
     delete pins;
     if (report_stmt_stats_) {
@@ -581,16 +583,17 @@ VerilogReader::makeModuleInst(const char *module_name,
       inst_lib_count_++;
       inst_lib_net_arrays_ += port_count;
     }
+    return inst;
   }
   else {
-    inst = new VerilogModuleInst(module_name, inst_name, pins, line);
+    VerilogInst *inst = new VerilogModuleInst(module_name, inst_name, pins, line);
     if (report_stmt_stats_) {
       inst_module_names_ += strlen(module_name) + 1;
       inst_names_ += strlen(inst_name) + 1;
       inst_mod_count_++;
     }
+    return inst;
   }
-  return inst;
 }
 
 bool