write_verilog -remove_cells

include/sta/VerilogWriter.hh

@@ -16,6 +16,8 @@
 
 #pragma once
 
+#include "LibertyClass.hh"
+
 namespace sta {
 
 class Network;
@@ -23,6 +25,7 @@ class Network;
 void
 writeVerilog(const char *filename,
 	     bool sort,
+	     LibertyCellSeq *remove_cells,
 	     Network *network);
 
 } // namespace

tcl/Cmds.tcl

@@ -1145,6 +1145,12 @@ proc parse_libcell_libport_inst_port_pin_edge_timing_arc_set_arg { objects \
     edges timing_arc_sets
 }
 
+proc parse_libcell_arg { objects } {
+  set libcells {}
+  get_object_args $objects {} libcells {} {} {} {} {} {} {} {}
+  return $libcells
+}
+
 proc parse_libcell_inst_arg { objects libcells_var insts_var } {
   upvar 1 $libcells_var libcells
   upvar 1 $insts_var insts

tcl/StaTcl.i

@@ -429,6 +429,10 @@ using namespace sta;
   Tcl_SetObjResult(interp, list);
 }
 
+%typemap(in) LibertyCellSeq* {
+  $1 = tclListSeqLibertyCell($input, interp);
+}
+
 %typemap(out) TmpCellSeq* {
   Tcl_Obj *list = Tcl_NewListObj(0, nullptr);
   CellSeq *cells = $1;

verilog/Verilog.i

@@ -25,6 +25,7 @@
 using sta::Sta;
 using sta::NetworkReader;
 using sta::readVerilogFile;
+using sta::LibertyCellSeq;
 
 %}
 
@@ -51,13 +52,14 @@ delete_verilog_reader()
 
 void
 write_verilog_cmd(const char *filename,
-		  bool sort)
+		  bool sort,
+		  LibertyCellSeq *remove_cells)
 {
   // This does NOT want the SDC (cmd) network because it wants
   // to see the sta internal names.
   Sta *sta = Sta::sta();
   Network *network = sta->network();
-  writeVerilog(filename, sort, network);
+  writeVerilog(filename, sort, remove_cells, network);
 }
 
 %} // inline

verilog/Verilog.tcl

@@ -19,15 +19,19 @@ namespace eval sta {
 # Defined by SWIG interface Verilog.i.
 define_cmd_args "read_verilog" {filename}
 
-define_cmd_args "write_verilog" {[-sort] filename}
+define_cmd_args "write_verilog" {[-sort] [-remove_cells cells] filename}
 
 proc write_verilog { args } {
-  parse_key_args "write_verilog" args keys {} flags {-sort}
+  parse_key_args "write_verilog" args keys {-remove_cells} flags {-sort}
 
+  set remove_cells {}
+  if { [info exists keys(-remove_cells)] } {
+    set remove_cells [sta::parse_libcell_arg $keys(-remove_cells)]
+  }
   set sort [info exists flags(-sort)]
   check_argc_eq1 "write_verilog" $args
   set filename $args
-  write_verilog_cmd $filename $sort
+  write_verilog_cmd $filename $sort $remove_cells
 }
 
 # sta namespace end

verilog/VerilogWriter.cc

@@ -32,6 +32,7 @@ class VerilogWriter
 public:
   VerilogWriter(const char *filename,
 		bool sort,
+		LibertyCellSeq *remove_cells,
 		FILE *stream,
 		Network *network);
   void writeModule(Instance *inst);
@@ -54,6 +55,7 @@ protected:
 
   const char *filename_;
   bool sort_;
+  CellSet remove_cells_;
   FILE *stream_;
   Network *network_;
 
@@ -65,12 +67,13 @@ protected:
 void
 writeVerilog(const char *filename,
 	     bool sort,
+	     LibertyCellSeq *remove_cells,
 	     Network *network)
 {
   if (network->topInstance()) {
     FILE *stream = fopen(filename, "w");
     if (stream) {
-      VerilogWriter writer(filename, sort, stream, network);
+      VerilogWriter writer(filename, sort, remove_cells, stream, network);
       writer.writeModule(network->topInstance());
       fclose(stream);
     }
@@ -81,6 +84,7 @@ writeVerilog(const char *filename,
 
 VerilogWriter::VerilogWriter(const char *filename,
 			     bool sort,
+			     LibertyCellSeq *remove_cells,
 			     FILE *stream,
 			     Network *network) :
   filename_(filename),
@@ -89,6 +93,8 @@ VerilogWriter::VerilogWriter(const char *filename,
   network_(network),
   unconnected_net_index_(1)
 {
+  for(LibertyCell *lib_cell : *remove_cells)
+    remove_cells_.insert(network->cell(lib_cell));
 }
 
 void
@@ -205,23 +211,25 @@ void
 VerilogWriter::writeChild(Instance *child)
 {
   Cell *child_cell = network_->cell(child);
-  const char *child_name = network_->name(child);
-  const char *child_vname = instanceVerilogName(child_name,
-						network_->pathEscape());
-  fprintf(stream_, " %s %s (",
-	  network_->name(child_cell),
-	  child_vname);
-  bool first_port = true;
-  CellPortIterator *port_iter = network_->portIterator(child_cell);
-  while (port_iter->hasNext()) {
-    Port *port = port_iter->next();
-    if (network_->hasMembers(port)) 
-      writeInstBusPin(child, port, first_port);
-    else 
-      writeInstPin(child, port, first_port);
+  if (!remove_cells_.hasKey(child_cell)) {
+    const char *child_name = network_->name(child);
+    const char *child_vname = instanceVerilogName(child_name,
+						  network_->pathEscape());
+    fprintf(stream_, " %s %s (",
+	    network_->name(child_cell),
+	    child_vname);
+    bool first_port = true;
+    CellPortIterator *port_iter = network_->portIterator(child_cell);
+    while (port_iter->hasNext()) {
+      Port *port = port_iter->next();
+      if (network_->hasMembers(port)) 
+	writeInstBusPin(child, port, first_port);
+      else 
+	writeInstPin(child, port, first_port);
+    }
+    delete port_iter;
+    fprintf(stream_, ");\n");
   }
-  delete port_iter;
-  fprintf(stream_, ");\n");
 }
 
 void