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verilog black box ports unknown/loads 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2021-09-17 08:35:45 -07:00
parent 41706e0db6
commit 85f437bc59
2 changed files with 5 additions and 3 deletions
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4
network/Network.cc
View File

@ -521,7 +521,9 @@ Network::isLoad(const Pin *pin) const
const Instance *inst = instance(pin);
return (isLeaf(inst) && dir->isAnyInput())
// isTopLevelPort(pin)
|| (isTopInstance(inst) && dir->isAnyOutput());
|| (isTopInstance(inst) && dir->isAnyOutput())
// Black box unknown ports are treated as loads.
|| dir->isUnknown();
}
bool

4
verilog/VerilogReader.cc
View File

@ -2058,7 +2058,7 @@ VerilogReader::makeBlackBoxNamedPorts(Cell *cell,
Port *port = (size == 1)
? network_->makePort(cell, port_name)
: network_->makeBusPort(cell, port_name, 0, size - 1);
network_->setDirection(port, PortDirection::bidirect());
network_->setDirection(port, PortDirection::unknown());
}
}
@ -2077,7 +2077,7 @@ VerilogReader::makeBlackBoxOrderedPorts(Cell *cell,
? network_->makePort(cell, port_name)
: network_->makeBusPort(cell, port_name, size - 1, 0);
stringDelete(port_name);
network_->setDirection(port, PortDirection::bidirect());
network_->setDirection(port, PortDirection::unknown());
port_index++;
}
}