sta::worst_slack args, sta to verilog name args

tcl/Search.tcl

@@ -318,21 +318,36 @@ define_hidden_cmd_args "worst_negative_slack" \
   {[-corner corner] [-min]|[-max]}
 
 proc worst_negative_slack { args } {
-  parse_key_args "total_negative_slack" args \
+  set worst_slack [worst_slack1 "worst_negative_slack" $args]
+  if { $worst_slack < 0.0 } {
+    return $worst_slack
+  } else {
+    return 0.0
+  }
+}
+
+################################################################
+
+define_hidden_cmd_args "worst_slack" \
+  {[-corner corner] [-min]|[-max]}
+
+proc worst_slack { args } {
+  return [worst_slack1 "worst_slack" $args]
+}
+
+# arg parsing common to worst_slack/worst_negative_slack
+proc worst_slack1 { cmd args1 } {
+  parse_key_args $cmd args1 \
     keys {-corner} flags {-min -max}
-  check_argc_eq0 "worst_negative_slack" $args
+  check_argc_eq0 $cmd $args1
   set min_max [parse_min_max_flags flags]
   if { [info exists keys(-corner)] } {
     set corner [parse_corner_required keys]
     set worst_slack [worst_slack_corner $corner $min_max]
   } else {
-    set worst_slack [worst_slack $min_max]
-  }
-  if { $worst_slack < 0.0 } {
-    return [time_sta_ui $worst_slack]
-  } else {
-    return 0.0
+    set worst_slack [worst_slack_cmd $min_max]
   }
+  return [time_sta_ui $worst_slack]
 }
 
 ################################################################

tcl/Sta.tcl

@@ -492,7 +492,7 @@ proc_redirect report_tns {
     set digits $sta_report_default_digits
   }
 
-  puts "tns [format %.${digits}f [total_negative_slack]]"
+  puts "tns [format_time [total_negative_slack_cmd "max"] $digits]"
 }
 
 ################################################################
@@ -510,7 +510,29 @@ proc_redirect report_wns {
     set digits $sta_report_default_digits
   }
 
-  puts "wns [format %.${digits}f [worst_negative_slack]]"
+  set slack [worst_slack_cmd "max"]
+  if { $slack > 0.0 } {
+    set slack 0.0
+  }
+  puts "wns [format_time $slack $digits]"
+}
+
+################################################################
+
+define_sta_cmd_args "report_worst_slack" { [-digits digits]}
+
+proc_redirect report_worst_slack {
+  global sta_report_default_digits
+
+  parse_key_args "report_worst_slack" args keys {-digits} flags {}
+  if [info exists keys(-digits)] {
+    set digits $keys(-digits)
+    check_positive_integer "-digits" $digits
+  } else {
+    set digits $sta_report_default_digits
+  }
+
+  puts "worst slack [format_time [worst_slack_cmd "max"] $digits]"
 }
 
 ################################################################

tcl/StaTcl.i

@@ -4546,7 +4546,7 @@ total_negative_slack_corner_cmd(const Corner *corner,
 }
 
 Slack
-worst_slack(const MinMax *min_max)
+worst_slack_cmd(const MinMax *min_max)
 {
   cmdLinkedNetwork();
   Sta *sta = Sta::sta();

verilog/Verilog.hh

@@ -160,8 +160,14 @@ public:
   void reportStmtCounts();
   const char *constant10Max() const { return constant10_max_; }
   size_t constant10MaxLength() const { return constant10_max_length_; }
+  const char *
+  verilogName(VerilogModuleInst *inst);
+  const char *
+  instanceVerilogName(const char *inst_name);
+  const char *
+  netVerilogName(const char *net_name);
 
-private:
+protected:
   DISALLOW_COPY_AND_ASSIGN(VerilogReader);
   void init(const char *filename);
   void makeCellPorts(Cell *cell,

verilog/VerilogReader.cc

@@ -755,6 +755,25 @@ VerilogReader::warn(const char *filename,
   va_end(args);
 }
 
+const char *
+VerilogReader::verilogName(VerilogModuleInst *mod_inst)
+{
+  return sta::instanceVerilogName(mod_inst->instanceName(),
+				  network_->pathEscape());
+}
+
+const char *
+VerilogReader::instanceVerilogName(const char *inst_name)
+{
+  return sta::netVerilogName(inst_name, network_->pathEscape());
+}
+
+const char *
+VerilogReader::netVerilogName(const char *net_name)
+{
+  return sta::netVerilogName(net_name, network_->pathEscape());
+}
+
 ////////////////////////////////////////////////////////////////
 
 VerilogModule::VerilogModule(const char *name,
@@ -827,9 +846,9 @@ VerilogModule::parseDcl(VerilogDcl *dcl,
 	dcl_map_[net_name] = dcl;
       else if (!dcl->direction()->isInternal())
 	reader->warn(filename_, dcl->line(),
-		      "signal %s previously declared on line %d.\n",
-		      net_name,
-		      existing_dcl->line());
+		     "signal %s previously declared on line %d.\n",
+		     reader->netVerilogName(net_name),
+		     existing_dcl->line());
     }
     else
       dcl_map_[net_name] = dcl;
@@ -854,7 +873,7 @@ VerilogModule::checkInstanceName(VerilogInst *inst,
     } while (inst_names.findKey(replacement_name));
     reader->warn(filename_, inst->line(),
 		 "instance name %s duplicated - renamed to %s.\n",
-		 inst_name,
+		 reader->instanceVerilogName(inst_name),
 		 replacement_name);
     inst_name = replacement_name;
     inst->setInstanceName(inst_name);
@@ -1733,7 +1752,8 @@ VerilogReader::linkNetwork(Cell *top_cell,
       return top_instance;
   }
   else {
-    report->error("%s is not a verilog module.\n", network_->name(top_cell));
+    report->error("%s is not a verilog module.\n",
+		  network_->name(top_cell));
     return nullptr;
   }
 }
@@ -1793,13 +1813,13 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
       linkWarn(filename_, mod_inst->line(),
 	       "module %s not found.  Creating black box for %s.\n",
 	       mod_inst->moduleName(),
-	       mod_inst->instanceName());
+	       verilogName(mod_inst));
     }
     else
       linkError(filename_, mod_inst->line(),
 		"module %s not found for instance %s.\n",
 		mod_inst->moduleName(),
-		mod_inst->instanceName());
+		verilogName(mod_inst));
   }
   if (cell) {
     Instance *inst = network_->makeInstance(cell, mod_inst->instanceName(),
@@ -1852,7 +1872,7 @@ VerilogReader::makeNamedInstPins(Cell *cell,
 	  && network_->size(port) != vpin->size(parent_module))
 	linkWarn(parent_module->filename(), mod_inst->line(),
 		 "instance %s port %s size %d does not match net size %d.\n",
-		 mod_inst->instanceName(),
+		 verilogName(mod_inst),
 		 network_->name(port),
 		 network_->size(port),
 		 vpin->size(parent_module));
@@ -1875,11 +1895,12 @@ VerilogReader::makeNamedInstPins(Cell *cell,
 	delete net_name_iter;
       }
     }
-    else
+    else {
       linkWarn(parent_module->filename(), mod_inst->line(),
 	       "instance %s port %s not found.\n",
-	       mod_inst->instanceName(),
+	       verilogName(mod_inst),
 	       port_name);
+    }
   }
 }
 
@@ -1901,7 +1922,7 @@ VerilogReader::makeOrderedInstPins(Cell *cell,
     if (network_->size(port) != net->size(parent_module))
       linkWarn(parent_module->filename(), mod_inst->line(),
 	       "instance %s port %s size %d does not match net size %d.\n",
-	       mod_inst->instanceName(),
+	       verilogName(mod_inst),
 	       network_->name(port),
 	       network_->size(port),
 	       net->size(parent_module));

verilog/VerilogWriter.cc

@@ -183,7 +183,8 @@ VerilogWriter::writeChild(Instance *child)
 {
   Cell *child_cell = network_->cell(child);
   const char *child_name = network_->name(child);
-  const char *child_vname = instanceVerilogName(child_name, '\0');
+  const char *child_vname = instanceVerilogName(child_name,
+						network_->pathEscape());
   fprintf(stream_, " %s %s (",
 	  network_->name(child_cell),
 	  child_vname);
@@ -194,7 +195,7 @@ VerilogWriter::writeChild(Instance *child)
     Net *net = network_->net(pin);
     if (net) {
       const char *net_name = network_->name(net);
-      const char *net_vname = netVerilogName(net_name, '\0');
+      const char *net_vname = netVerilogName(net_name, network_->pathEscape());
       Port *port = network_->port(pin);
       const char *port_name = network_->name(port);
       if (!first)