link_design use verilog library to lookup top

CMakeLists.txt

@@ -384,7 +384,7 @@ set(STA_HEADERS
   util/Vector.hh
   util/Zlib.hh
   
-  verilog/Verilog.hh
+  verilog/VerilogReaderPvt.hh
   verilog/VerilogReader.hh
   verilog/VerilogWriter.hh
   )

network/ConcreteNetwork.cc

@@ -1841,15 +1841,8 @@ ConcreteNetwork::linkNetwork(const char *top_cell_name,
   if (link_func_) {
     clearConstantNets();
     deleteTopInstance();
-    Cell *top_cell = findAnyCell(top_cell_name);
-    if (top_cell) {
-      top_instance_ = link_func_(top_cell, make_black_boxes, report, this);
-      return top_instance_ != nullptr;
-    }
-    else {
-      report->error("cell %s not found.\n", top_cell_name);
-      return false;
-    }
+    top_instance_ = link_func_(top_cell_name, make_black_boxes, report, this);
+    return top_instance_ != nullptr;
   }
   else {
     report->error("cell type %s can not be linked.\n", top_cell_name);

network/Network.hh

@@ -35,7 +35,7 @@ typedef Set<const Net*> ConstNetSet;
 typedef Map<const char*, LibertyLibrary*, CharPtrLess> LibertyLibraryMap;
 // Link network function returns top level instance.
 // Return nullptr if link fails.
-typedef Instance *(LinkNetworkFunc)(Cell *top_cell,
+typedef Instance *(LinkNetworkFunc)(const char *top_cell_name,
 				    bool make_black_boxes,
 				    Report *report,
 				    NetworkReader *network);

verilog/VerilogLex.ll

@@ -19,7 +19,7 @@
 #include "Machine.hh"
 #include "Debug.hh"
 #include "VerilogNamespace.hh"
-#include "Verilog.hh"
+#include "VerilogReaderPvt.hh"
 #include "VerilogParse.hh"
 
 #define YY_NO_INPUT

verilog/VerilogParse.yy

@@ -19,7 +19,7 @@
 #include <stdlib.h>
 #include "Machine.hh"
 #include "PortDirection.hh"
-#include "Verilog.hh"
+#include "VerilogReaderPvt.hh"
 #include "VerilogReader.hh"
 
 int VerilogLex_lex();

verilog/VerilogReader.cc

@@ -25,7 +25,7 @@
 #include "Liberty.hh"
 #include "Network.hh"
 #include "VerilogNamespace.hh"
-#include "Verilog.hh"
+#include "VerilogReaderPvt.hh"
 #include "VerilogReader.hh"
 
 extern int
@@ -47,7 +47,7 @@ hierarchyLevel(Net *net,
 	       Network *network);
 // Return top level instance.
 Instance *
-linkVerilogNetwork(Cell *top_cell,
+linkVerilogNetwork(const char *top_cell_name,
 		   bool make_black_boxes,
 		   Report *report,
 		   NetworkReader *network);
@@ -1684,10 +1684,12 @@ VerilogNetPortRefPart::name()
 ////////////////////////////////////////////////////////////////
 
 Instance *
-linkVerilogNetwork(Cell *top_cell, bool make_black_boxes,
-		   Report *report, NetworkReader *)
+linkVerilogNetwork(const char *top_cell_name,
+		   bool make_black_boxes,
+		   Report *report,
+		   NetworkReader *)
 {
-  return verilog_reader->linkNetwork(top_cell, make_black_boxes, report);
+  return verilog_reader->linkNetwork(top_cell_name, make_black_boxes, report);
 }
 
 // Verilog net name to network net map.
@@ -1715,10 +1717,11 @@ private:
 };
 
 Instance *
-VerilogReader::linkNetwork(Cell *top_cell,
+VerilogReader::linkNetwork(const char *top_cell_name,
 			   bool make_black_boxes,
 			   Report *report)
 {
+  Cell *top_cell = network_->findCell(library_, top_cell_name);
   VerilogModule *module = verilog_reader->module(top_cell);
   if (module) {
     // Seed the recursion for expansion with the top level instance.

verilog/VerilogReaderPvt.hh

@@ -141,7 +141,7 @@ public:
 					  int from_index,
 					  int to_index);
   VerilogModule *module(Cell *cell);
-  Instance *linkNetwork(Cell *top_cell,
+  Instance *linkNetwork(const char *top_cell_name,
 			bool make_black_boxes,
 			Report *report);
   int line() const { return line_; }