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create separate nand cells for user drc sky130 cell

This commit is contained in:
Jesse Cirimelli-Low 2026-05-14 16:21:29 -07:00
parent cc9f294992
commit 541b744e82
7 changed files with 34 additions and 3 deletions
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technology/sky130/gds_lib/sky130_custom_nand2_dec.gds Normal file
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technology/sky130/gds_lib/sky130_custom_nand3_dec.gds Normal file
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technology/sky130/gds_lib/sky130_custom_nand4_dec.gds Normal file
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technology/sky130/sp_lib/sky130_custom_nand2_dec.sp Normal file
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@ -0,0 +1,8 @@
* NGSPICE file created from sky130_fd_bd_sram__openram_sp_custom_nand2_dec.ext - technology: sky130A
.subckt sky130_custom_nand2_dec A B Z VDD GND
X0 Z A VDD VDD sky130_fd_pr__pfet_01v8 w=1.12 l=0.15
X1 VDD B Z VDD sky130_fd_pr__pfet_01v8 w=1.12 l=0.15
X2 a_196_224# B GND GND sky130_fd_pr__nfet_01v8 w=0.74 l=0.15
X3 Z A a_196_224# GND sky130_fd_pr__nfet_01v8 w=0.74 l=0.15
.ends

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technology/sky130/sp_lib/sky130_custom_nand3_dec.sp Normal file
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* Top level circuit sky130_fd_bd_sram__openram_sp_custom_nand3_dec
.subckt sky130_custom_nand3_dec A B C Z VDD GND
X1001 Z A a_n346_328# GND sky130_fd_pr__nfet_01v8 W=0.74u L=0.15u m=1
X1002 a_n346_256# C GND GND sky130_fd_pr__nfet_01v8 W=0.74u L=0.15u m=1
X1003 a_n346_328# B a_n346_256# GND sky130_fd_pr__nfet_01v8 W=0.74u L=0.15u m=1
X1000 Z B VDD VDD sky130_fd_pr__pfet_01v8 W=1.12u L=0.15u m=1
X1004 Z A VDD VDD sky130_fd_pr__pfet_01v8 W=1.12u L=0.15u m=1
X1005 Z C VDD VDD sky130_fd_pr__pfet_01v8 W=1.12u L=0.15u m=1
.ends

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technology/sky130/sp_lib/sky130_custom_nand4_dec.sp Normal file
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* NGSPICE file created from sky130_fd_bd_sram__openram_sp_custom_nand4_dec.ext - technology: sky130A
.subckt sky130_custom_nand4_dec A B C D Z VDD GND
X0 VDD C Z VDD sky130_fd_pr__pfet_01v8 w=1.12u l=0.15u
X1 a_n384_98# C a_128_208# GND sky130_fd_pr__nfet_01v8 w=0.74u l=0.15u
X2 Z D VDD VDD sky130_fd_pr__pfet_01v8 w=1.12u l=0.15u
X3 Z B VDD VDD sky130_fd_pr__pfet_01v8 w=1.12u l=0.15u
X4 a_128_136# A Z GND sky130_fd_pr__nfet_01v8 w=0.74u l=0.15u
X5 VDD A Z VDD sky130_fd_pr__pfet_01v8 w=1.12u l=0.15u
X6 a_128_208# B a_128_136# GND sky130_fd_pr__nfet_01v8 w=0.74u l=0.15u
X7 GND D a_n384_98# GND sky130_fd_pr__nfet_01v8 w=0.74u l=0.15u
.ends

6
technology/sky130/tech/tech_configs/tech_custom_cell.py
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@ -226,9 +226,9 @@ cell_properties.write_driver.port_map = {'din': 'DIN',
# If it is a list, the first is single port and the second is dual port.
# If it is string, it is used for both single and dual port.
cell_properties.names["dff"] = "sky130_fd_bd_sram__openram_dff"
cell_properties.names["nand2_dec"] = ["sky130_fd_bd_sram__openram_dp_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
cell_properties.names["nand3_dec"] = ["sky130_fd_bd_sram__openram_dp_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
cell_properties.names["nand4_dec"] = ["sky130_fd_bd_sram__openram_dp_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
cell_properties.names["nand2_dec"] = ["sky130_custom_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
cell_properties.names["nand3_dec"] = ["sky130_custom_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
cell_properties.names["nand4_dec"] = ["sky130_custom_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
cell_properties.names["bitcell_1port"] = "sky130_custom_cell"
cell_properties.names["replica_bitcell_1port"] = "sky130_custom_replica"