mirror of https://github.com/VLSIDA/OpenRAM.git
remove debug print statements
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9fcf61f031
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@ -68,8 +68,6 @@ class dummy_array(bitcell_base_array):
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core_block[(0 + r) % 2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[(1 + r) % 2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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print(core_block)
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#print(r, c)
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#print(core_block)
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@ -35,7 +35,6 @@ class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_b
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for row_end in self.dummy_col_insts:
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row_end = row_end.mod
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print(self.get_all_wordline_names(), row_end.get_wordline_names())
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for (rba_wl_name, wl_name) in zip(self.get_all_wordline_names(), row_end.get_wordline_names()):
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pin = row_end.get_pin(wl_name)
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self.add_layout_pin(text=rba_wl_name,
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