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add tech fix

This commit is contained in:
FriedrichWu 2024-12-21 18:57:06 +01:00
parent 474a240f38
commit 74cab87782
1 changed files with 5 additions and 2 deletions
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7
technology/sky130/tech/tech.py
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@ -502,7 +502,8 @@ drc["pwell_to_nwell"] = 0
drc.add_layer("nwell",
width=0.840,
spacing=1.270)
# nwell.6 Minimum enclosure of nwell hole by deep nwell outside UHVI
drc["minclosure_nwell_by_dnwell"] = 1.030
# poly.1a Minimum width of poly
# poly.2 Minimum spacing of poly AND active
drc.add_layer("poly",
@ -662,7 +663,8 @@ drc.add_enclosure("m3",
drc.add_layer("via3",
width=0.200,
spacing=0.200)
# via3.12 Minimum spacing of via3 to via2 (cu)
drc["via3_to_via2"] = 0.180
# m4.1 Minimum width of metal4
# m4.2 Minimum spacing of metal4
# m4.7 Minimum area of metal4
@ -748,6 +750,7 @@ spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
spice["dff_leakage"] = 1 # Leakage power of flop in nW