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fix naming for spare cols

This commit is contained in:
Jesse Cirimelli-Low 2026-06-24 11:27:28 -07:00
parent e16d9eb0b4
commit 734be5403e
1 changed files with 6 additions and 1 deletions
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7
compiler/modules/sram_1bank.py
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@ -662,7 +662,12 @@ class sram_1bank(design, verilog, lef):
inputs = []
outputs = []
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
# The top-level pin is a scalar (spare_wen{port}) when there is
# a single spare column, so drop the 1-bit bus index to match it.
if self.num_spare_cols == 1:
inputs.append("spare_wen{}".format(port))
else:
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)