mirror of https://github.com/VLSIDA/OpenRAM.git
single port fixes
This commit is contained in:
Jesse Cirimelli-Low
parent
4ce6e0538b
commit
5a74605117
2
Makefile
2
Makefile
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@ -13,7 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git
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# Use this for development
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#SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git
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#SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
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SRAM_LIB_GIT_COMMIT ?= 9bb620d12ae380dfe38f9a68df809f068f7b2a21
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SRAM_LIB_GIT_COMMIT ?= 32f553d240545574282ac437ff98d2b889bf039f
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SKY130_PDK ?= $(PDK_ROOT)/sky130A
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GF180_PDK ?= $(PDK_ROOT)/gf180mcuD
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@ -19,7 +19,7 @@ class bitcell_array(bitcell_base_array):
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Creates a rows x cols array of memory cells.
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Assumes bit-lines and word lines are connected by abutment.
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"""
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def __init__(self, rows, cols, column_offset=0, name=""):
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def __init__(self, rows, cols, column_offset=0, name="", left_rbl=None, right_rbl=None):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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@ -78,7 +78,9 @@ class replica_bitcell_array(bitcell_base_array):
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self.bitcell_array = factory.create(module_type="bitcell_array",
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column_offset=len(self.left_rbl),
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cols=self.column_size,
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rows=self.row_size)
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rows=self.row_size,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl)
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# Replica bitlines
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self.replica_columns = {}
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@ -833,8 +833,8 @@ Xrca_top_4
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X0 ll WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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X1 ul Q_bar_float VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X2 BL WL ul VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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X5 VPWR Q_float lr VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X6 ur Q_bar_float VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X7 VGND Q_float ll VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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@ -977,8 +977,8 @@ Xrca_19
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X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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@ -989,8 +989,8 @@ X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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@ -833,8 +833,8 @@ Xrca_top_4
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X0 ll WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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X1 ul Q_bar_float VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X2 BL WL ul VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X3 ur WL ur VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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*X4 lr WL lr VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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X5 VPWR Q_float lr VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X6 ur Q_bar_float VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X7 VGND Q_float ll VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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@ -977,8 +977,8 @@ Xrca_19
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X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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@ -989,8 +989,8 @@ X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X0 Q_bar WL BR VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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X1 Q Q_bar VGND VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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X2 BL WL Q VNB sky130_fd_pr__special_nfet_pass w=0.14 l=0.15
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.07 l=0.095
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*X3 Q WL Q VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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*X4 Q_bar WL Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14u l=25n
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X5 VPWR Q Q_bar VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X6 Q Q_bar VPWR VPB sky130_fd_pr__special_pfet_pass w=0.14 l=0.15
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X7 VGND Q Q_bar VNB sky130_fd_pr__special_nfet_latch w=0.21 l=0.15
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@ -23,6 +23,10 @@ class sky130_bitcell(bitcell_base):
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cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1"
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elif version == "opt1a":
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cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1a"
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elif version == "opt1_noblcon":
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cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon"
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elif version == "opt1a_noblcon":
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cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon"
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else:
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debug.error("Invalid sky130 cell name", -1)
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@ -19,14 +19,18 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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Creates a rows x cols array of memory cells.
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Assumes bit-lines and word lines are connected by abutment.
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"""
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def __init__(self, rows, cols, column_offset=0, name=""):
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def __init__(self, rows, cols, column_offset=0, name="",left_rbl=None, right_rbl=None):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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def add_modules(self):
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""" Add the modules used in this design """
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# Bitcell for port names only
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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self.cella = factory.create(module_type=OPTS.bitcell, version="opt1a")
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#self.cell_noblcon = factory.create(module_type=OPTS.bitcell, version="opt1_noblcon")
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#self.cella_noblcon = factory.create(module_type=OPTS.bitcell, version="opt1a_noblcon")
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
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self.strapa = factory.create(module_type="internal", version="wlstrapa")
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@ -36,6 +40,9 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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""" Create the module instances used in this design """
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self.all_inst={}
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self.cell_inst={}
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#self.cell_noblcon_inst = geometry.instance("cell_noblcon_inst", mod=self.cell_noblcon, is_bitcell=True)
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#self.cella_noblcon_inst = geometry.instance("cella_noblcon_inst", mod=self.cella_noblcon, is_bitcell=True)
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bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \
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+ [geometry.instance("01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]\
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@ -46,11 +53,32 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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+ [geometry.instance("11_strap_p", mod=self.strap_p, is_bitcell=False)] \
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+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("13_strapa", mod=self.strapa, is_bitcell=False)]
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bit_block = []
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pattern.append_row_to_block(bit_block, bit_row_opt1)
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pattern.append_row_to_block(bit_block, bit_row_opt1a)
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for row in bit_block:
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row = pattern.rotate_list(row, self.column_offset * 2)
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self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="bit_r{0}_c{1}")
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self.pattern.connect_array()
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# for i in range(len(self.insts)):
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# if self.left_rbl:
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# if "r{}".format(self.row_size-1) in self.insts[i].name:
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# if self.insts[i].mod == self.cell:
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# self.insts[i].mod = self.cell_noblcon_inst.mod
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# self.insts[i].gds = self.cell_noblcon_inst.gds
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# elif self.insts[i].mod == self.cella:
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# self.insts[i].mod = self.cella_noblcon_inst.mod
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# self.insts[i].gds = self.cella_noblcon_inst.gds
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# if self.right_rbl:
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# if "r{}".format("0") in self.insts[i].name:
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# if self.insts[i].mod == self.cell:
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# self.insts[i].mod = self.cell_noblcon_inst.mod
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# self.insts[i].gds = self.cell_noblcon_inst.gds
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# elif self.insts[i].mod == self.cella:
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# self.insts[i].mod = self.cella_noblcon_inst.mod
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# self.insts[i].gds = self.cella_noblcon_inst.gds
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@ -50,9 +50,9 @@ class sky130_dummy_array(dummy_array, sky130_bitcell_base_array):
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bit_block = []
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if(self.row_offset % 2 == 0):
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next_row = 0
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else:
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next_row = 1
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else:
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next_row = 0
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for i in range(self.row_size):
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if next_row == 0:
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@ -814,7 +814,9 @@ flatglob = ["*_?mos_m*",
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blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
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"sky130_fd_bd_sram__openram_dp_cell_dummy",
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"sky130_fd_bd_sram__openram_dp_cell_replica",
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"sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon",
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"sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon",
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"sky130_fd_bd_sram__openram_sp_colend_replica",
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"sky130_fd_bd_sram__openram_sp_colenda_replica",
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"sky130_fd_bd_sram__sram_sp_cell_opt1a",
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