luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

add fix for cypress sp wls

This commit is contained in:
Jesse Cirimelli-Low 2026-04-28 17:19:54 -07:00
parent 5077282180
commit 88241ca685
8 changed files with 35 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
compiler/modules/bitcell_base_array.py
View File

@ -121,13 +121,15 @@ class bitcell_base_array(design):
def get_all_wordline_names(self, port=None):
""" Return all the wordline names """
temp = []
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
if len(self.all_ports) > 0:
temp.extend(self.get_rbl_wordline_names(0))
if port == None:
temp.extend(self.all_wordline_names)
else:
temp.extend(self.wordline_names[port])
temp.extend(self.get_rbl_wordline_names(0))
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
return temp

2
compiler/modules/row_cap_array.py
View File

@ -103,7 +103,7 @@ class row_cap_array(bitcell_base_array):
max_row = self.row_size - 2
for row in range(0, max_row):
for port in self.all_ports:
wl_pin = self.cell_inst[max_row - 1 - row, 0].get_pin(wl_names[port])
wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
layer=wl_pin.layer,
offset=wl_pin.ll().scale(0, 1),

29
technology/sky130/custom/sky130_bitcell_array.py
View File

@ -19,11 +19,12 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
Creates a rows x cols array of memory cells.
Assumes bit-lines and word lines are connected by abutment.
"""
def __init__(self, rows, cols, column_offset=0, row_offset=0, name="",left_rbl=None, right_rbl=None):
def __init__(self, rows, cols, column_offset=0, row_offset=0, name="", left_rbl=None, right_rbl=None):
super().__init__(rows=rows, cols=cols, column_offset=column_offset, row_offset=row_offset, name=name)
self.left_rbl = left_rbl
self.right_rbl = right_rbl
self.column_offset = column_offset
self.row_offset = row_offset
def add_modules(self):
""" Add the modules used in this design """
# Bitcell for port names only
@ -44,19 +45,23 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
#self.cell_noblcon_inst = geometry.instance("cell_noblcon_inst", mod=self.cell_noblcon, is_bitcell=True)
#self.cella_noblcon_inst = geometry.instance("cella_noblcon_inst", mod=self.cella_noblcon, is_bitcell=True)
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \
+ [geometry.instance("01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]\
+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True, mirror='MX')] \
+ [geometry.instance("03_strap", mod=self.strap, is_bitcell=False, mirror='MX')]
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='MX')] \
+ [geometry.instance("01_strap_p", mod=self.strap, is_bitcell=False, mirror='MX')]\
+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \
+ [geometry.instance("03_strap", mod=self.strap_p, is_bitcell=False, mirror='MX')]
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True, mirror='MY')] \
+ [geometry.instance("11_strap_p", mod=self.strap_p, is_bitcell=False)] \
+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \
+ [geometry.instance("13_strapa", mod=self.strapa, is_bitcell=False)]
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \
+ [geometry.instance("11_strapa", mod=self.strap, is_bitcell=False)] \
+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True, mirror='MY')] \
+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)]
bit_block = []
pattern.append_row_to_block(bit_block, bit_row_opt1)
pattern.append_row_to_block(bit_block, bit_row_opt1a)
if self.row_offset % 2 == 0:
pattern.append_row_to_block(bit_block, bit_row_opt1)
pattern.append_row_to_block(bit_block, bit_row_opt1a)
else:
pattern.append_row_to_block(bit_block, bit_row_opt1a)
pattern.append_row_to_block(bit_block, bit_row_opt1)
for row in bit_block:
row = pattern.rotate_list(row, self.column_offset * 2)

1
technology/sky130/custom/sky130_capped_replica_bitcell_array.py
View File

@ -35,6 +35,7 @@ class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_b
for row_end in self.dummy_col_insts:
row_end = row_end.mod
print(self.get_all_wordline_names(), row_end.get_wordline_names())
for (rba_wl_name, wl_name) in zip(self.get_all_wordline_names(), row_end.get_wordline_names()):
pin = row_end.get_pin(wl_name)
self.add_layout_pin(text=rba_wl_name,

16
technology/sky130/custom/sky130_dummy_array.py
View File

@ -37,15 +37,15 @@ class sky130_dummy_array(dummy_array, sky130_bitcell_base_array):
self.all_inst={}
self.cell_inst={}
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MY')] \
+ [geometry.instance("01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='')]\
+ [geometry.instance("02_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='')] \
+ [geometry.instance("03_strap", mod=self.strap, is_bitcell=False, mirror='')]
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')] \
+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False, mirror='MX')]\
+ [geometry.instance("02_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')] \
+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cella, is_bitcell=True, mirror='MY')] \
+ [geometry.instance("11_strap_p", mod=self.strap_p, is_bitcell=False)] \
+ [geometry.instance("12_opt1a", mod=self.dummy_cella, is_bitcell=True)] \
+ [geometry.instance("13_strapaa", mod=self.strapa, is_bitcell=False)]
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cella, is_bitcell=True, mirror='')] \
+ [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False, mirror='')] \
+ [geometry.instance("12_opt1a", mod=self.dummy_cella, is_bitcell=True, mirror='MY')] \
+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False, mirror='')]
bit_block = []

4
technology/sky130/custom/sky130_replica_bitcell_array.py
View File

@ -26,7 +26,7 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
Requires a regular bitcell array, replica bitcell, and dummy
bitcell (Bl/BR disconnected).
"""
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
def __init__(self, rows=0, cols=0, rbl=None, left_rbl=None, right_rbl=None, column_offset=0, row_offset=0, name="",):
debug.check((cols+ sum(rbl)) % 2==0, "must have an even number of cols including replica cols; you can add a spare col to fix this")
super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
super().__init__(rows, cols, rbl, left_rbl, right_rbl, column_offset, row_offset, name)

2
technology/sky130/custom/sky130_replica_column.py
View File

@ -64,7 +64,7 @@ class sky130_replica_column(replica_column, sky130_bitcell_base_array):
+ [geometry.instance("dummy_13_strapa", mod=self.strapa, is_bitcell=False)]
bit_block = []
if self.column_offset % 2 == 0:
if self.column_offset % 2 == 1:
replica_row_opt1 = replica_row_opt1[0:2]
replica_row_opt1a = replica_row_opt1a[0:2]
dummy_row_opt1 = dummy_row_opt1[0:2]

8
technology/sky130/custom/sky130_row_cap_array.py
View File

@ -90,15 +90,7 @@ class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array):
strap_pins.append("gnd") # vnb
return strap_pins
def create_all_wordline_names(self, row_size=None, start_row=0):
if row_size == None:
row_size = self.row_size
for row in range(start_row, row_size):
for port in self.all_ports:
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
def create_layout(self):