mirror of https://github.com/VLSIDA/OpenRAM.git
add io placer
This commit is contained in:
FriedrichWu
parent
6743049d44
commit
20e454925a
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base.vector import vector
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from openram.base.vector3d import vector3d
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from openram import OPTS
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from .graph import graph
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from .graph_shape import graph_shape
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from .router import router
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import re
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class io_pin_placer(router):
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"""
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This is the signal escape router that uses the Hanan grid graph method.
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"""
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def __init__(self, layers, design, bbox=None):
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# `router` is the base router class
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router.__init__(self, layers, design, bbox)
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# New pins are the side supply pins
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self.new_pins = {}
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# added_io_pins
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self.io_pins_added_left = []
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self.io_pins_added_right = []
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self.io_pins_added_up = []
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self.io_pins_added_down = []
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def get_closest_edge(self, point):
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""" Return a point's the closest edge and the edge's axis direction. """
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ll, ur = self.bbox
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# Snap the pin to the perimeter and break the iteration
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ll_diff_x = abs(point.x - ll.x)
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ll_diff_y = abs(point.y - ll.y)
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ur_diff_x = abs(point.x - ur.x)
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ur_diff_y = abs(point.y - ur.y)
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min_diff = min(ll_diff_x, ll_diff_y, ur_diff_x, ur_diff_y)
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if min_diff == ll_diff_x:
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return "left", True
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if min_diff == ll_diff_y:
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return "bottom", False
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if min_diff == ur_diff_x:
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return "right", True
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return "top", False
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def create_fake_pin(self, pin):
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""" Create a fake pin on the perimeter orthogonal to the given pin. """
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ll, ur = self.bbox
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c = pin.center()
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print("inside pin name")
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print("----------------------------------------------------------")
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print(pin.name)
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# Find the closest edge
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edge, vertical = self.get_closest_edge(c)
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offset = 0.95 + 0.19 # FIX: this is the magic number to overcome the ovetflow problem at the boundary, may need a method
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add_distance = 0
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# Keep the fake pin out of the SRAM layout are so that they won't be
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# blocked by previous signals if they're on the same orthogonal line
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if edge == "left":
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fake_center = vector(ll.x - self.track_wire * 2 + offset, c.y)
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is_too_close = any(abs(pin_added.center().y - fake_center.y) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_left)
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while is_too_close:
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debug.warning("overlap, changing position")
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add_distance = add_distance + 0.8 + self.half_wire * 4
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fake_center = vector(ll.x - self.track_wire * 2 + offset, c.y + add_distance)
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is_too_close = any(abs(pin_added.center().y - fake_center.y) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_left)
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if edge == "bottom":
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fake_center = vector(c.x, ll.y - self.track_wire * 2 + offset)
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is_too_close = any(abs(pin_added.center().x - fake_center.x) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_down)
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while is_too_close:
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debug.warning("overlap, changing position")
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add_distance = add_distance + 0.8 + self.half_wire * 4
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fake_center = vector(c.x + add_distance, ll.y - self.track_wire * 2 + offset)
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is_too_close = any(abs(pin_added.center().x - fake_center.x) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_down)
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if edge == "right":
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fake_center = vector(ur.x + self.track_wire * 2 - offset, c.y)
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is_too_close = any(abs(pin_added.center().y - fake_center.y) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_right)
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while is_too_close:
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debug.warning("overlap, changing position")
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add_distance = add_distance + 0.8 + self.half_wire * 4
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fake_center = vector(ur.x + self.track_wire * 2 - offset, c.y + add_distance)
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# debug
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for pin_added in self.io_pins_added_right:
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dis = abs(pin_added.center().y - fake_center.y)
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debug.warning("current position is {0}".format(fake_center))
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debug.warning("distance from {0} is {1}".format(pin_added, dis))
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debug.warning("must disrance is {0}".format(0.8 + self.half_wire * 4))
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is_too_close = any(abs(pin_added.center().y - fake_center.y) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_right)
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if edge == "top":
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fake_center = vector(c.x, ur.y + self.track_wire * 2 - offset)
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is_too_close = any(abs(pin_added.center().x - fake_center.x) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_up)
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while is_too_close:
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debug.warning("overlap, changing position")
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add_distance = add_distance + 0.8 + self.half_wire * 4
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fake_center = vector(c.x + add_distance, ur.y + self.track_wire * 2 - offset)
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is_too_close = any(abs(pin_added.center().x - fake_center.x) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_up)
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# Create the fake pin shape
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layer = self.get_layer(int(not vertical))
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half_wire_vector = vector([self.half_wire] * 2)
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nll = fake_center - half_wire_vector - half_wire_vector
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nur = fake_center + half_wire_vector + half_wire_vector
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rect = [nll, nur]
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pin = graph_shape(name=pin.name + "_" + "fake",
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rect=rect,
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layer_name_pp=layer)
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print("this create_fake_pin")
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print(pin.name)
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print(pin.center)
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if edge == "left":
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self.io_pins_added_left.append(pin)
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elif edge == "bottom":
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self.io_pins_added_down.append(pin)
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elif edge == "right":
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self.io_pins_added_right.append(pin)
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elif edge == "top":
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self.io_pins_added_up.append(pin)
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debug.warning("pin added: {0}".format(pin))
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return pin
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def add_io_pins(self, pin_names):
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""" Add IO pins on the edges without routing them. """
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debug.info(1, "Adding IO pins on the perimeter...")
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# Prepare GDS reader (if necessary for pin/blockage identification)
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self.prepare_gds_reader()
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# Find pins to be added (without routing)
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for name in pin_names:
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self.find_pins(name)# this will add the pins to the self.pins
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# Replace layout pins with those on the perimeter
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for name in self.pins:
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pin = next(iter(self.pins[name]))
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fake_pin = self.create_fake_pin(pin)
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self.design.replace_layout_pin(name, fake_pin) # if do not have replace_layout_pin, final gds won't have io pins
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def remove_io_pins(self, pin_name):
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# remove io pin in gds, so we could reroute
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self.design.remove_layout_pin(pin_name)
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import os
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import shutil
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import datetime
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from openram import debug
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from openram import sram_config as config
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from openram import OPTS, print_time
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class sram():
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"""
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This is not a design module, but contains an SRAM design instance.
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It could later try options of number of banks and organization to compare
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results.
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We can later add visualizer and other high-level functions as needed.
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"""
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def __init__(self, sram_config=None, name=None):
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# Create default configs if custom config isn't provided
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if sram_config is None:
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sram_config = config(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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write_size=OPTS.write_size,
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num_banks=OPTS.num_banks,
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words_per_row=OPTS.words_per_row,
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num_spare_rows=OPTS.num_spare_rows,
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num_spare_cols=OPTS.num_spare_cols)
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if name is None:
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name = OPTS.output_name
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sram_config.set_local_config(self)
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# reset the static duplicate name checker for unit tests
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# in case we create more than one SRAM
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from openram.base import design
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design.name_map=[]
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debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
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self.num_words,
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self.num_banks))
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start_time = datetime.datetime.now()
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self.name = name
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from openram.modules.sram_openroad import sram_1bank as sram
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#from openram.modules.sram_new import sram_1bank as sram
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self.s = sram(name, sram_config)
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self.s.create_netlist()
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if not OPTS.netlist_only:
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self.s.create_layout_openroad()
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if not OPTS.is_unit_test:
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print_time("SRAM creation", datetime.datetime.now(), start_time)
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def get_sp_name(self):
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if OPTS.use_pex:
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# Use the extracted spice file
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return self.pex_name
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else:
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# Use generated spice file for characterization
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return self.sp_name
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def sp_write(self, name, lvs=False, trim=False):
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self.s.sp_write(name, lvs, trim)
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def lef_write(self, name):
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self.s.lef_write(name)
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def gds_write(self, name):
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self.s.gds_write(name)
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def verilog_write(self, name):
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self.s.verilog_write(name)
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if self.num_banks != 1:
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from openram.modules.sram_multibank import sram_multibank
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mb = sram_multibank(self.s)
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mb.verilog_write(name[:-2] + '_top.v')
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def extended_config_write(self, name):
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"""Dump config file with all options.
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Include defaults and anything changed by input config."""
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f = open(name, "w")
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var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
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for var_name, var_value in var_dict.items():
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if isinstance(var_value, str):
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f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
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else:
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f.write(str(var_name) + " = " + str(var_value)+ "\n")
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f.close()
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def save_only(self):
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.s.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.s.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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# Import this at the last minute so that the proper tech file
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# is loaded and the right tools are selected
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from openram import verify
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from openram.characterizer import functional
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from openram.characterizer import delay
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.s.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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# Save a functional simulation file with default period
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functional(self.s,
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spname,
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cycles=200,
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output_path=OPTS.output_path)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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# Save stimulus and measurement file
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start_time = datetime.datetime.now()
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debug.print_raw("DELAY: Writing stimulus...")
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d = delay(self.s, spname, ("TT", 5, 25), output_path=OPTS.output_path)
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if (self.s.num_spare_rows == 0):
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probe_address = "1" * self.s.addr_size
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else:
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probe_address = "0" + "1" * (self.s.addr_size - 1)
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probe_data = self.s.word_size - 1
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d.analysis_init(probe_address, probe_data)
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d.targ_read_ports.extend(self.s.read_ports)
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d.targ_write_ports = [self.s.write_ports[0]]
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d.write_delay_stimulus()
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print_time("DELAY", datetime.datetime.now(), start_time)
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# Save trimmed spice file
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temp_trim_sp = "{0}trimmed.sp".format(OPTS.output_path)
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self.sp_write(temp_trim_sp, lvs=False, trim=True)
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.s.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.s.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
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debug.print_raw("LVS: Writing to {0}".format(lvsname))
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self.sp_write(lvsname, lvs=True)
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if not OPTS.netlist_only and OPTS.check_lvsdrc:
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verify.write_lvs_script(cell_name=self.s.name,
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gds_name=os.path.basename(gdsname),
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sp_name=os.path.basename(lvsname),
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("LVS writing", datetime.datetime.now(), start_time)
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# Save the extracted spice file
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if OPTS.use_pex:
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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pexname = OPTS.output_path + self.s.name + ".pex.sp"
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spname = OPTS.output_path + self.s.name + ".sp"
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verify.run_pex(self.s.name, gdsname, spname, output=pexname)
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sp_file = pexname
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print_time("Extraction", datetime.datetime.now(), start_time)
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else:
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# Use generated spice file for characterization
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sp_file = spname
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# Characterize the design
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start_time = datetime.datetime.now()
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from openram.characterizer import lib
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debug.print_raw("LIB: Characterizing... ")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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# Write the config file
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start_time = datetime.datetime.now()
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try:
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from shutil import copyfile
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copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
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except shutil.SameFileError:
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pass
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debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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print_time("Config", datetime.datetime.now(), start_time)
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# Write the datasheet
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start_time = datetime.datetime.now()
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from openram.datasheet import datasheet_gen
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dname = OPTS.output_path + self.s.name + ".html"
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debug.print_raw("Datasheet: Writing to {0}".format(dname))
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datasheet_gen.datasheet_write(dname)
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print_time("Datasheet", datetime.datetime.now(), start_time)
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# Write a verilog model
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start_time = datetime.datetime.now()
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vname = OPTS.output_path + self.s.name + '.v'
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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# Write out options if specified
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if OPTS.output_extended_config:
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start_time = datetime.datetime.now()
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oname = OPTS.output_path + OPTS.output_name + "_extended.py"
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debug.print_raw("Extended Config: Writing to {0}".format(oname))
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self.extended_config_write(oname)
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print_time("Extended Config", datetime.datetime.now(), start_time)
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Reference in New Issue