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OpenRAM
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all sky130 crba passing

This commit is contained in:
Jesse Cirimelli-Low 2026-04-28 23:22:40 -07:00
parent 88241ca685
commit 2780fda35c
3 changed files with 5 additions and 3 deletions
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1
technology/sky130/custom/sky130_dummy_array.py
View File

@ -25,6 +25,7 @@ class sky130_dummy_array(dummy_array, sky130_bitcell_base_array):
""" Add the modules used in this design """
self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1")
self.dummy_cella = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
self.strap = factory.create(module_type="internal", version="wlstrap")
self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
self.strapa = factory.create(module_type="internal", version="wlstrapa")

4
technology/sky130/custom/sky130_dummy_bitcell.py
View File

@ -21,9 +21,9 @@ class sky130_dummy_bitcell(bitcell_base):
# Ignore the name argument
if version == "opt1":
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_dummy"
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon"
elif version == "opt1a":
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon"
super().__init__(name, cell_name, prop=props.bitcell_1port)
debug.info(2, "Create dummy bitcell")

3
technology/sky130/tech/tech_configs/tech_cypress_cell.py
View File

@ -845,4 +845,5 @@ blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
"sky130_fd_bd_sram__sram_sp_wlstrap",
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce",
"sky130_fd_bd_sram__sram_sp_wlstrap_p"]
"sky130_fd_bd_sram__sram_sp_wlstrap_p",
"sky130_fd_bd_sram__sram_sp_wlstrapa_p"]