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allow tech file to specify connection to power rail per net

This commit is contained in:
Jesse Cirimelli-Low 2026-05-06 10:42:02 -07:00
parent 541d4ff572
commit e7829cf641
5 changed files with 51 additions and 27 deletions
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33
compiler/modules/capped_replica_bitcell_array.py
View File

@ -11,6 +11,8 @@ from openram.sram_factory import factory
from openram.tech import drc, spice
from openram.tech import cell_properties as props
from openram.tech import connect_ring_bottom, connect_ring_left, connect_ring_right, connect_ring_top
from openram.tech import power_ring_top, power_ring_bottom, power_ring_left, power_ring_right
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
@ -250,7 +252,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height))
self.supply_rail_width = drc["minwidth_m3"]
self.supply_rail_pitch = 6 * self.supply_rail_width
self.add_power_ring(v_layer=v_layer, h_layer=h_layer)
self.add_power_ring(v_layer=v_layer, h_layer=h_layer, top=power_ring_top, bottom=power_ring_bottom, left=power_ring_left, right=power_ring_right)
def get_main_array_top(self):
return self.replica_bitcell_array_inst.by() + self.replica_bitcell_array.get_main_array_top()
@ -339,12 +341,13 @@ class capped_replica_bitcell_array(bitcell_base_array):
bitcell = factory.create(module_type="pbitcell")
else:
bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
top = connect_ring_top
bottom = connect_ring_bottom
left = connect_ring_left
right = connect_ring_right
if top:
if 'vdd' in top:
inst = self.dummy_row_insts[1]
if 'vdd' in inst.mod.pins:
array_pins = inst.get_pins('vdd')
@ -354,7 +357,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(array_pin.center()[0], supply_pin.center()[1]))
if 'gnd' in top:
inst = self.dummy_row_insts[1]
if 'gnd' in inst.mod.pins:
array_pins = inst.get_pins('gnd')
for array_pin in array_pins:
supply_pin = self.top_gnd_pin
@ -362,7 +367,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(array_pin.center()[0], supply_pin.center()[1]))
if bottom:
if 'vdd' in bottom:
inst = self.dummy_row_insts[0]
if 'vdd' in inst.mod.pins:
array_pins = inst.get_pins('vdd')
@ -372,7 +377,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(array_pin.center()[0], supply_pin.center()[1]))
if 'gnd' in bottom:
inst = self.dummy_row_insts[0]
if 'gnd' in inst.mod.pins:
array_pins = inst.get_pins('gnd')
for array_pin in array_pins:
supply_pin = self.bottom_gnd_pin
@ -380,17 +387,19 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(array_pin.center()[0], supply_pin.center()[1]))
if left:
if 'vdd' in left:
inst = self.dummy_col_insts[0]
if 'vnd' in inst.mod.pins:
array_pins = inst.get_pins('vnd')
if 'vdd' in inst.mod.pins:
array_pins = inst.get_pins('vdd')
for array_pin in array_pins:
supply_pin = self.left_vdd_pin
self.add_path(array_pin.layer, [array_pin.center(), vector(supply_pin.center()[0], array_pin.center()[1])])
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(supply_pin.center()[0], array_pin.center()[1]))
if 'gnd' in left:
inst = self.dummy_col_insts[0]
if 'gnd' in inst.mod.pins:
array_pins = inst.get_pins('gnd')
for array_pin in array_pins:
supply_pin = self.left_gnd_pin
@ -398,7 +407,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(supply_pin.center()[0], array_pin.center()[1]))
if right:
if 'vdd' in right:
inst = self.dummy_col_insts[1]
if 'vdd' in inst.mod.pins:
array_pins = inst.get_pins('vdd')
@ -408,7 +417,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.add_via_stack_center(from_layer = array_pin.layer,
to_layer = supply_pin.layer,
offset = vector(supply_pin.center()[0], array_pin.center()[1]))
if 'gnd' in right:
inst = self.dummy_col_insts[1]
if 'gnd' in inst.mod.pins:
array_pins = inst.get_pins('gnd')
for array_pin in array_pins:
supply_pin = self.right_gnd_pin

13
technology/freepdk45/tech/tech.py
View File

@ -44,10 +44,15 @@ cell_properties.bitcell_2port.mirror.y = False
###################################################
layer_properties = d.layer_properties()
connect_ring_top = False
connect_ring_bottom = False
connect_ring_left = True
connect_ring_right = True
power_ring_top = True
power_ring_bottom = True
power_ring_left = True
power_ring_right = True
connect_ring_top = []
connect_ring_bottom = []
connect_ring_left = ['vdd','gnd']
connect_ring_right = ['vdd','gnd']
###################################################
# GDS file info
###################################################

12
technology/scn4m_subm/tech/tech.py
View File

@ -107,10 +107,14 @@ lef_rom_interconnect = ["m1", "m2", "m3", "m4"]
# Use M3/M4
power_grid = m3_stack
connect_ring_top = False
connect_ring_bottom = False
connect_ring_left = True
connect_ring_right = True
power_ring_top = True
power_ring_bottom = True
power_ring_left = True
power_ring_right = True
connect_ring_top = ['gnd']
connect_ring_bottom = ['gnd']
connect_ring_left = ['vdd']
connect_ring_right = ['vdd']
###################################################
##GDS Layer Map
###################################################

12
technology/sky130/tech/tech_configs/tech_custom_cell.py
View File

@ -248,10 +248,14 @@ array_col_multiple = 2
###################################################
# Power grid
###################################################
connect_ring_top = True
connect_ring_bottom = True
connect_ring_left = False
connect_ring_right = False
power_ring_top = True
power_ring_bottom = True
power_ring_left = True
power_ring_right = True
connect_ring_top = ['vdd','gnd']
connect_ring_bottom = ['vdd','gnd']
connect_ring_left = []
connect_ring_right = []
###################################################
# Custom layer properties

8
technology/sky130/tech/tech_configs/tech_cypress_cell.py
View File

@ -276,10 +276,10 @@ layer_properties.global_wordline_layer = "m5"
###################################################
# Power grid
###################################################
connect_ring_top = True
connect_ring_bottom = True
connect_ring_left = False
connect_ring_right = False
connect_ring_top = ['vdd','gnd']
connect_ring_bottom = ['vdd','gnd']
connect_ring_left = []
connect_ring_right = []
###################################################
# Discrete tx bins